Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms
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Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms Umer Farooq1
· Bander A. Alzahrani2
Received: 18 January 2020 / Accepted: 10 July 2020 © Springer-Verlag GmbH Austria, part of Springer Nature 2020
Abstract Recently, multi-FPGA platforms have become a popular choice to prototype complex digital systems. This is because of unique advantages such as high frequency and real world testing experience that are offered when compared to other pre-silicon testing techniques. However, one of several challenges faced by multi-FPGA prototyping is the requirement of an efficient back end flow. Partitioning is a key part of the back end flow of multi-FPGA systems and it directly affects the quality of final prototyped design. In this work, we explore two different partitioning approaches: one is multilevel; while the other is hierarchical partitioning approach. For experimentation, we use a suite of fourteen large benchmarks. Experimental results reveal that the multilevel approach gives 12.5% better frequency results for mono-cluster benchmarks while the hierarchical approach gives 13% better results for multi-cluster benchmarks. Furthermore, the hierarchical approach requires, on average, 60% less execution time when compared to the multilevel partitioning approach. Keywords Partitioning · Multi-FPGA systems · Prototyping Mathematics Subject Classification 05C70 · 68U07
1 Introduction Modern day System on Chip (SoC) designs have huge computation capability and they are enormously complex to design. Moreover, shrinking product life cycle and faster time-to-market pressures increase the need for an efficient, fault-free design process
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Umer Farooq [email protected] Bander A. Alzahrani [email protected]
1
Electrical and Computer Engineering Department, Dhofar University, Salalah, Oman
2
Faculty of Computing and Information Technology, King Abdulaziz University, Jeddah, Saudi Arabia
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U. Farooq, B. A. Alzahrani
[1,2]. Because a faulty and inefficient design can cost a huge fortune [3,4]. In this regard, FPGA-based prototyping offers a good option for complete design-to-silicon system verification. FPGA-based prototyping is pre-silicon verification technique that offers better speed as compared to simulation-based verification [5]. Simulation-based solutions are cost-effective but they are very slow and offer only abstract level view of the system. Although emulation-based pre-silicon verification gives good speed, unique feature of FPGA-based prototyping is that it gives real-world testing and trouble shooting experience to a user. Prototyping of less complex Application Specific Integrated Circuit (ASIC) can be performed on a single FPGA as the modern day FPGAs are quite capable and have huge logic capacity. However, as the complexity of the system under consideration grows, the capability of even the most modern FPGAs becomes insufficient to handle the resource and I/O requirement of the ASIC. For such scenarios, multi-FPGA platforms are required because the g
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