Fabrication and Properties of Single, Double, and Triple Gate Polycrystalline-Silicon Thin Film Transistors
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FABRICATION AND PROPERTIES OF SINGLE, DOUBLE, AND TRIPLE GATE POLYCRYSTALLINE-SILICON THIN FILM TRANSISTORS R.E. Proano*, R.J. Soave**, D.G. Ast*
*Department of Materials Science and Engineering, Bard Hall, Cornell University, Ithaca, N.Y.Nanofabrication 14853. "**National Facility, Knight Laboratory, Cornell University, Ithaca, N.Y. 14853 ABSTRACT
Polysilicon based Thin Film Transistors (poly-Si TFT's) with superior electrical performance can be achieved by maximizing the number of intrinsic point defect injected into the material during high temperature processing. These point defects will migrate to grain boundaries (GB's), enhance their mobility by facilitating climb, and allow the boundary to achieve a low energy configuration with a minimum of electrically active broken bonds. Proper processing of poly-Si TFT's therefore requires a redesign of the conventional processing cycle where, working with single crystal silicon, one minimizes the concentration of intrinsic point defects which otherwise precipitate out as Oxidation induced Stacking Faults (OSF's). TFT's were fabricated under nine different processing cycles to study the relationship between device performance and fabrication conditions. Device performance increased with higher gate oxidation temperature, elimination of HCI flow during gate oxidation, post hydrogenation, and multiple gates. Using conventional MOS processing steps only, n-type (p-type) devices were fabricated, which were capable of handling 40 volts VDS with a leakage current of 2x10-11 (6xl 0-12) A/lm and effective electron (hole) channel mobilities of 130 (50) cm2Ns. INTRODUCTION
TFT's are of interest in large area electronic applications such as flat pannel LCD's, image sensors, and print heads. They have been implemented in a variety of materials, such as amorphous silicon, polycrystalline silicon, laser recrystallized silicon, and cadmium selenide 1 . Polysilicon based TFT's have the advantage of being stable, are easily fabricated with conventional MOS equipment, and can be made with low leakage currents and high mobilities 2. The electrical properties of the poly-Si TFT's depend critically on the structure of the polycrystalline material. The research presented here was aimed in enhancing device performance by maximizing GB mobility during processing which, in turn, permits GB's to acquire a minimum energy configuration. This minimizes the electrical activity, resulting in higher carrier mobilities and fewer GB generation / recombination sites. DEVICE LAYOUT AND FABRICATION
Conventionally layed out TFT's with gate lengths (Lg) and widths (Lw) varying between 2 and 25 gIm, and with one to three gates, were fabricated using a selfaligned MOS type process. First, one micron of silicon dioxide was grown for insulation on three inch p-type silicon wafers. Next, the undoped channel
Mat. Res. Soc. Symp. Proc. Vol. 106.
1988 Materials Research Society
318
LPCVD polysilicon was deposited at 620 0C and 160 mtorr. It was then patterned into islands, and a 100oA gate oxide was grown
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