Fan-Out Wafer-Level Packaging, Springer (2018), pp. 303
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BOOK REVIEW
Fan‑Out Wafer‑Level Packaging, Springer (2018), pp. 303 ISBN: 9789811088834 (Print), 9789811088841 (Online) ISBN: 9789811088834 (Print), 9789811088841 (Online) Chong Leong Gan1 · Hem Takiar2 Received: 22 May 2020 / Accepted: 1 June 2020 © Society for Reliability and Safety (SRESA) 2020
Fan-Out Wafer-Level Packaging, by John. H, Lau presents good technical insights of fan-out level packaging theories and applications, which is suitable for both industry engineering and academic practitioners. The author provides insights on the broad values and technical applications of wafer level fan out packaging and reliability performances in this book. While the book is written as a standard technical reference textbook, it contains enough real-world references to highlight the book’s practicality, including real-world examples on fan-in and fan-out wafer and panel level packaging, 3D IC heterogenous integration and fan-out enabling technologies at the end of the book. The book’s opening chapter presents a good understanding and underscores the fundamentals of patent issues of fanout wafer-level packaging, supporting it with examples of patents impacting the semiconductor packaging. Flip chip technology versus fan-out wafer-level packaging (FOWLP) and fan-in wafer-level packaging (FIWLP) are discussed in next subsequent chapters. Also contained in next subsequent chapters encompasses few descriptions of the assembly process of fan-out wafer-level packaging: either by chip first, chip last or package-on-package (PoP), 3D integration and three-dimensional integrated circuits (3D IC) Heterogeneous Integration by FOWLP. The authors review the fundamental concepts of functional and level of semiconductor packaging, patents impacting semiconductor packaging, major claims of industrial patents, and ball, bump pitches, size of plastic ball grid array (PBGA), flip chip plastic ball grid array (fcPBGA) * Chong Leong Gan [email protected] 1
Micron Memory Taiwan, Co. Ltd, Taichung 42152, Taiwan
Micron Technology Inc., 110 Holger Way, San Jose, CA 95134, USA
2
and wafer-level chip scale package (WLCSP) in Chapter 1. Chapter 2 presents various assembly process flows and billof-materials of flip chip technology against FOWLP which includes flip chip package substrates, flip chip assembly process, underfill reliability, characteristics of pre- and post-underfill assembly, and Cu–Cu direct hybrid bonding technology. The common concepts of flip chip process and reliability are covered in Chapter 2. At the end of Chapter 2, summary of key comparisons and recommendations for future works is given. Chapter 3 lays out fan-in waferlevel packaging (FIWLP) against FOWLP, which comprises types of FIWLP, WLCSP, PCB Assembly of the WLCSP, and thermal cycling test of WLCSP-PCB assembly. The author discusses key fracture analysis of corner solder joints after temperature cycling which includes geometry of corner solder joints, elastic and plastic properties of corner solder joints, as well as its creep behavior. Few industrial WLCS
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