Faster-Than-At-Speed Test
Interconnect defects such as weak resistive opens, shorts and bridges increase the path delay affected by a pattern during manufacturing test but not significant enough to cause a failure at functional frequency. In this chapter, a new faster-than-at-spee
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Faster-Than-At-Speed Test
Interconnect defects such as weak resistive opens, shorts and bridges increase the path delay affected by a pattern during manufacturing test but not significant enough to cause a failure at functional frequency. In this chapter, a new faster-than-at-speed method is presented for delay test pattern application to screen small delay defects. Given a test pattern set, the technique groups the patterns into multiple sub-sets with close path delay distribution and determines an optimal test frequency considering both positive slack and performance degradation due to IR-drop effects. Since, the technique does not increase the test frequency to an extent that any paths exercised at the rated functional frequency may fail, it avoids any scan flip-flop masking. As most semiconductor companies currently deploy compression technologies to reduce test cost, scan cell masking is highly undesirable for pattern modification as it would imply pattern count increase and might result in pattern regeneration. Therefore, the solution presented in this chapter is more practical as the test engineer can run the same pattern set without any changes to the test flow other than the at-speed test frequency.
9.1 Introduction Technology scaling is introducing a larger population of timing-related defects in integrated circuits (ICs) and performance verification is becoming an ever more challenging problem. Transition delay fault model is widely practiced in industry to test such defects and is considered as a cost-effective alternative to functional pattern generation [1, 2]. Traditionally, transition delay fault tests were generated assuming gross delay defect size and fixed cycle time equivalent to the functional operating frequency for each clock domain. Under such assumptions, a delay defect will be detected only when it causes a transition to reach an observation point (primary output or scan flip-flop) by more than the positive slack of the affected path. Slack of a path is a measure of how close a transition on the respective path meets the timing to an observable point, relative to the test cycle time. M. Tehranipoor et al., Test and Diagnosis for Small-Delay Defects, DOI 10.1007/978-1-4419-8297-1 9, © Springer Science+Business Media, LLC 2011
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9 Faster-Than-At-Speed Test
Smaller technologies are introducing smaller delay defect sizes which may not necessarily cause a failure when detected through paths of any length. A delay defect that is not large enough to cause a timing failure under the fixed cycle time notion, regardless of the affected path length, is referred to as a small delay defect. A small delay defect might escape during test if is tested using a short path. While the same defect might be activated on a longer path during functional operation and it may cause a timing failure. Therefore, test coverage of small delay defects on long paths determines the quality of test patterns as these might cause immediate field failures. While, small delay defects on short paths might become a
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