Future Directions of Non-volatile Memory Technologies
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FUTURE DIRECTIONS OF NON-VOLATILE MEMORY TECHNOLOGIES ALBERT FAZIO INTEL CORPORATION SANTA CLARA, CA 95052, U.S.A.
ABSTRACT It expected that for many years to come, the majority of the nonvolatile memories shipped will be based on current mainstream flash technologies, which utilize transistor based charge storage memory cells and multi-level-cell concepts, for storing more than one logic bit in a single physical cell. Moore’s law will continue to drive transistor based memory technology scaling but technology complexity will be increasing. In order to meet technology scaling, the mainstream transistor based flash technologies will start evolving to incorporate material and structural innovations. This paper will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor based non-volatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor based flash memory cell can scale into the 32nm node. Further, more complex, structural innovations will be required to maintain further scaling. New memory concepts, not relying on transistors as a basis of the memory cell, provide new opportunities for future low cost memories. Several of these new concepts will be summarized and contrasted with the mainstream transistor based flash memory technologies. INTRODUCTION Floating gate flash memory1,2 is now the fastest growing memory segment, driven by the rapid growth of portable devices such as digital cameras and cellular phones. Flash memory is categorized by two basic approaches: NOR flash, characterized by fast initial access for high read performance, and NAND flash, characterized by slow initial access and high write performance. The first half of this paper will focus on scaling of NOR flash, however many of the scaling considerations described in this paper are common for both NOR and NAND floating gate flash memory. As flash memory devices begin to scale into the sub-100nm lithography regime, scaling is becoming challenged due to the high electric fields required for the programming and erase operations and the stringent leakage requirements for long term charge storage. These requirements are imposing fundamental scaling limitations on the cell operating voltages and on the physical thickness of the tunneling dielectric. Overcoming these limitations will require innovations in cell structure and device materials. This paper will outline the major scaling challenges for flash and identify some of the potential solutions to enable further scaling to occur. Flash Memory Scaling Challenges and Alternatives Figure 1 depicts the flash memory cell cross section and some of the major scaling constraints. The following sections explore how the introduction of new materials and structures will enable flash memory to continue scaling beyond simple linear extrapolations.
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