Generation of complex impedance for complex filter design using fully balanced current conveyors

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Generation of complex impedance for complex filter design using fully balanced current conveyors P. S. Veerendranath1 • Vivek Sharma1 • M. H. Vasantha1 • Y. B. Nithin Kumar1 Received: 20 September 2019 / Revised: 7 January 2020 / Accepted: 2 March 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020

Abstract In this paper a complex filter is presented where the shift in the frequency is obtained using a linear frequency transformation. The linear frequency transformation in the proposed design is implemented using a complex impedance. A complex impedance is also proposed in this paper using a Fully Balanced Second Generation Current Conveyor (FBCCII). The FBCCII design used in this paper consumes 84 lW of power and has an open loop gain of 47.83 dB with 62:9 of phase margin at 39.8 MHz unity gain bandwidth. A low power 3rd order complex filter is designed by linear frequency transformation at 40 MHz center frequency. The proposed complex filter achieves a bandwidth of 9 MHz with an image rejection ratio of 45 dB. The design consumes 1.5 mW of power and has a group delay of 12.5 ns. The figure of merit of the proposed filter is 0.007 fJ with a SFDR of 63.9 dB. The output noise of the design at 40 MHz center frequency is pffiffiffiffiffiffi 45:86 nV= Hz and integrated Input Referred noise is 600 lV. The design is simulated using a 180 nm CMOS technology with a supply voltage of  0:5 V. The circuit’s efficacy is verified and supported by PVT and post layout simulations. The area of the layout of the proposed design is 0:624 mm2 (i.e. 260 lm  240 lm). Keywords FBCCII  Low voltage  Complex filter  Linear frequency transformation  Complex impedance

1 Introduction The demand for integrated filters at the receiver front end is growing with the continuous development of communication systems, which leads to stringent filter design for frontend wireless applications [1]. The complexity of filter designs has been increasing with the implementation of digital designs for a wide range of wireless applications. The filter design imposes constraints on portability and performance of analog to digital converters (ADCs). This requirement needs to design the filter with low power as well as high performance metrics. Also, it should be implemented on the same chip without the need of high quality-factor Radio Frequency (RF) filters. The widely used architecture for wireless receivers are superheterodyne, Intermediate Frequency (IF) (e.g. Zero IF, Low IF and High IF). However, superheterodyne & P. S. Veerendranath [email protected] 1

Department of Electronics and Communication Engineering, National Institute of Technology, Ponda, Goa 403401, India

receivers posses serious limitations on channel selectivity, sensitivity and integration. This demands a need to design the filter with the low power consumption and cost with additional feature like on chip high quality factor. A complex filter had been designed in literature using a discrete time approach by employing four cascaded bandpass filters to implement