Gold in Flux-less Bonding: Noble or not Noble
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Gold in Flux-less Bonding: Noble or not Noble. Marco Balucani1, Paolo Nenzi1, Fabrizio Palma1, Hanna Bandarenka2, Leonid Dolgyi2, Aliksandr Shapel2 1 Department of Information Engineering, Electronics and Telecommunications, Sapienza – Università di Roma, Via Eudossiana, 18 – 00184 Roma (Italy) 2 Micro- and nano-electronics Department, Belarussian State University of Informatics and Radioelectronics, P. Brovka, 6 – 220027 Minsk, Belarus ABSTRACT This work highlights the solder joints reliability issues emerged during the development of a novel compliant contacting technology. The peculiar process in this technology is a mechanical lifting procedure in which a pulling force is exerted onto 63Sn-37Pb (eutectic) solder joints (realized by a flux-less thermo compression process), releasing metal traces from the substrate, to form free standing vertical structures. Since joints mechanical characteristics are critical for the successful fabrication of contacts, different bonding conditions (inert or forming atmosphere, temperature rates) and surface finishing (electroplated gold and preformed solder) have been tested. SEM and EDX analyses have been performed on failing joints to investigate failure causes and classify defect typologies. A constantly higher failure rate (percent number of failing joints) has been observed on gold finished surfaces. Analyses proved that such unusual rate was due to contamination of gold surface left by additives in the plating bath and to the embrittlement caused by gold diffusion into molten solder. Plating additives contamination reduces the wettability of gold surfaces. Concentration values of 3 wt.% for gold, considered safe for surface mount applications, caused embrittlement in solder bumps of 20-40 μm diameters. INTRODUCTION The continuous scaling of integrated circuit features affects the dimensions of bonding pads and their pitch. This in turn requires that packaging and probing technologies scales as well. Recently a construction of a novel compliant contacting technology [1] applicable to both integrated circuits testing (wafer level probe card) and packaging was proposed [2]. In the assembly steps of the technology, the silicon substrate holding the metal wires forming the contacting structures is bonded to a ceramic (alumina) substrate holding the signal redistribution layer by means of 63Sn-37Pb solder in a thermo-compression process. Once bonded, the metal wires are released from the substrate “pulling” the two substrates away and keeping them at a prescribed distance. The space between the two substrates (enclosing free-standing wires) is filled with a thermoset polymer by capillarity. As the polymer is cured, the silicon substrate is removed by XeF2 etching in order to expose the metal wire ends (the contacting tips). Solder joint design In this technology the solder joint is subject to a pulling force exerted to release the metal wire from the substrate where it has been plated. The adhesion between substrate and metal has to be carefully controlled to ensure separation of
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