GS/s AD Conversion for Broadband Multi-stream Reception
In this paper we present a fully integrated solution for broadband multi-stream reception, based on the direct sampling receiver architecture. The key enabler of such a solution is a 64-times interleaved 2.6 GS/s 10 b Successive-Approximation-Register ADC
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GS/s AD Conversion for Broadband Multi-stream Reception Erwin Janssen, Athon Zanikopoulos, Kostas Doris, Claudio Nani, and Gerard van der Weide
Abstract In this paper we present a fully integrated solution for broadband multi-stream reception, based on the direct sampling receiver architecture. The key enabler of such a solution is a 64-times interleaved 2.6 GS/s 10 b Successive-Approximation-Register ADC. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. It is used in a fully integrated direct sampling receiver for DOCSIS 3.0 including a digital multichannel selection filter and a PLL. The ADC achieves an SNDR of 48.5 dB and a THD of less than 58 dB at Nyquist with an input signal of 1.4Vpp diff. It consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm2 in 65 nm CMOS.
4.1
Introduction
During the last years we are witnessing an increasing demand for higher data throughput rates over cable networks. The introduction of the DOCSIS 3.0 standard enabled this increase by means of channel bonding, realizing a total throughput rate of 152 Mb/s [1]. A straightforward DOCSIS 3.0 compliant receiver implementation, which uses a traditional structure, results in excess power consumption (1.6 W) [2]. Another solution [3] presents a limited dual tuner solution, since it operates on two 32 MHz bands instead of receiving a single block of 64 MHz. This fully analog dual tuner approach allows for more flexibility in the cable frequency planning, but it is not easily scalable for higher number of channels. For every additional channel it requires the complete RF processing chain, including the LO
E. Janssen (*) • A. Zanikopoulos • K. Doris • G. van der Weide NXP Semiconductors, High Speed Data Acquisition - office 2.20, High Tech Campus 32, 5656AE Eindhoven, NL, The Netherlands e-mail: [email protected] C. Nani Marvell, Pavia, Italy A.H.M. van Roermund et al. (eds.), Nyquist AD Converters, Sensor Interfaces, and Robustness: Advances in Analog Circuit Design, 2012, DOI 10.1007/978-1-4614-4587-6_4, # Springer Science+Business Media New York 2013
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Fig. 4.1 Direct sampling receiver for cable applications
generation, to be duplicated. The use of this architecture to fulfill the market trend (full frequency flexibility with 16þ channels) is therefore considered challenging. The solution presented in this work is a full spectrum receiver (FSR) that digitizes the complete cable band, spanning from 48 MHz to 1,002 MHz (Fig. 4.1). This direct sampling approach is scalable to down convert many RF channels, e.g. 16–32, in a power and area efficient way by only expanding the digital part of the chip while keeping the same analog frontend. An essential advantage of the direct RF sampling receiver is that it doesn’t suffer from local oscillator (LO) harmonics and image problems, typical issues for receivers involving mixers. Moreover, having captured the entire cable band, it is easy to scale the number of ch
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