High Electric Field Breakdown of 4H-SiC pn Junction Diodes

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Mat. Res. Soc. Symp. Proc. Vol. 423 01996 Materials Research Society

and p-type dopants respectively. The 5 mm x 5 mm substrates were degreased by immersing in trichloroethylene, acetone, methanol and deionized water. The samples were then treated with buffered-oxide-etch solution to remove any surface oxide layer before being loaded into the growth chamber. Epitaxial n- and p-type epilayers were grown at atmospheric pressure at about 145015000C. Circular device structures with diameter ranging from 50-300 gtm were then patterned on the samples by a two-mask photolithographic process. The first mask enabled the formation of mesa structures by reactive-ion-etching using pure NF3 gas. The p-n junctions were then passivated by an oxide layer of about 600 A thick which was grown by thermal oxidation at about 1100°C. This oxide layer was then patterned using the second mask followed by treatment with buffered-oxide-etch (BOE) solution to expose the top surface of the mesa structures for subsequent metallization. The metallization step consisted of sputtering - 2000 A Ni on the back followed by annealing at 950'C for 5 minutes to form the back ohmic contact. The front contact was made by sputtering - 2000 A AMTi and annealed at 1150°C for 10 s. A schematic drawing of the diode is shown in figure 1. Al

SO

AMTi p+

-0.3

ipm

p-

3.0 gm

n

-5.0 pm

n+

Ni

Figure 1. 4H-SiC p-n diode mesa structure with oxide passivation. Doping concentration (cm-3): n -8x101 5 ; p = -5x10

7

; p÷= -5x10

19

; n+= -5x0'I8 .

For high electric field measurements, the p-n junction diode was connected in a reverse bias mode to a specially constructed high voltage ramp generator, which is capable of supplying a negative going ramp voltage pulse of variable slope as well as variable pulse duration. The experiment involved applying a single ramp voltage pulse which gradually increased the bias across the device while the current through the device was being monitored until breakdown current appeared. The advantage of this technique is that breakdown mechanisms due to field-induced thermal effects can be excluded from the study. RESULTS The time resolved voltage and current characteristics corresponding to some typical diode structures are shown in figure 2. The broken line in each graph is the ramp voltage pulse. The actual slope and pulse width of the ramp voltage can be deduced from the figure. Since the applied ramp voltage has a constant slope (dV/dt), the measured current has a displacement current component proportional to the capacitance of the depletion region at the reverse biased junction, along with a leakage current component due to the generation processes in the device. The combination of these two components produces the characteristic current profile as shown in figure 2. The characteristic

112

current profile can be explained as follows. At low voltages, the current is observed to decay from an initial peak value (labeled A in figure 2a) in a somewhat exponential manner as expected from the reduction in the displacement

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