High growth rate 3C-SiC growth: from hetero-epitaxy to homo-epitaxy
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High growth rate 3C-SiC growth: from hetero-epitaxy to homo-epitaxy F. La Via1, G. Litrico1, R. Anzalone2, A. Severino2, M. Salanitri2, S. Coffa2 1 2
IMM-CNR, VIII Strada 5, 95121, Catania, Italy
STMicroelectronics, Stradale Primosole 50, 95121, Catania, Italy
Abstract 3C-SiC devices are hampered by a high crystal defect density due to the hetero-epitaxial growth of these films, which results in the presence of stacking faults (SF). In this paper high growth rate CVD processes have been used to try to reduce the SF density in 3C-SiC films. In a first step a high growth rate (30 Pm/h) has been used to grow 50 Pm thick 3C-SiC layer on (100) Si. Then the silicon substrate was removed via etching and a further 3C-SiC growth was performed with a higher growth rate (90 Pm/h) at a higher temperature (1600 °C) to obtain a final thickness of 150 Pm. The SF presence and density were evaluated by TEM analysis performed on as-grown samples and SEM analysis on KOH etched samples with various thicknesses. A decrease of SF density was observed with an increase of 3C-SiC film thickness, with the best results (500/cm) obtained for the thickest sample. The 3C-SiC film quality and orientation was evaluated by XRD are correlated with film thickness and SF density. Introduction Cubic Silicon Carbide (3C-SiC) is regarded as a most promising candidate for high power and high frequency device applications since 3C-SiC displays the highest speed of electron transport within the crystal of all of the SiC polytypes [1]. The growth of thick 3C-SiC layers can be extremely interesting for the realization of power devices below a breakdown voltage of 800 V where DC-DC converters and DC-AC inverters are needed for electric vehicles or hybrid cars. To overcome this limitation, silicon power devices are typically used for this important application but it is necessary to use very heavy and expensive heat sinks to reduce the device temperature (due to the high currents) because of the low band gap and low thermal conductivity of the silicon substrate. For these applications, 3C-SiC is the ideal material because it has high channel mobility with almost the same characteristics of the hexagonal polytypes [2]. Furthermore, one important property of 3C–SiC is that it can be grown on large diameter Si (silicon) substrates. This property is very attractive since the homo-epitaxial growth of SiC is influenced by the limited diameter of commercially available SiC substrates, with the present availability of a maximum of 6 inch diameter 4H– and 6H–SiC substrates. However, the growth of 3C– SiC on Si substrates is affected by intrinsic problems of the hetero-epitaxial growth such as the mismatch in the lattice parameters and/or the thermal expansion coefficients between two dissimilar materials. The large lattice mismatch, which is about 20% (aSiC=0.436 nm, aSi=0.543 nm), is one of the most serious causes in the generation of stacking faults and/or cracks. One of the main limitations for device fabrication on 3C-SiC comes from the wafer fabrication. Further
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