High-Performance Poly-Si TFTs with Multiple Selectively Doped Regions in the Active Layer
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High-Performance Poly-Si TFTs With Multiple Selectively Doped Regions In The Active Layer Min-Cheol Lee, Juhn-Suk Yoo, Kee-Chan Park, Sang-Hoon Jung, Min-Koo Han, and Hyun-Jae Kim*
School of Electrical Engineering, Seoul National University, Seoul, 151-742, KOREA AMLCD division, Samsung Electronics, Kyung-gi Do, KOREA* ABSTRACT We have proposed and fabricated a new poly-Si TFT that employs selectively doped regions between the source and drain in order to reduce leakage current without the sacrifice of the on current. In the proposed poly-Si TFTs, the selectively doped regions where doping concentration is identical to that of source/drain, reduce the effective channel length during the on state. Under the off state, the selectively doped regions may reduce the lateral electric field induced in the depletion region near drain so that the leakage current reduces considerably. The experimental data of the proposed TFT shows that it has the high on-current, low leakage current and low threshold voltage when compared with conventional TFT. The fabrication steps for the proposed TFT are reduced because ion-implantation for source/drain and selectively doped regions is performed simultaneously prior to an excimer laser irradiation. It should be noted that, in the proposed TFT, only one excimer laser annealing is required while two excimer laser annealing steps are required in conventional TFT. INTRODUCTION In the active matrix liquid crystal display (AMLCD) application, low temperature poly-Si thin-film transistors (TFTs) fabricated by excimer laser annealing have been widely investigated due to high mobility and integration of pixel and peripheral circuit on the inexpensive glass substrate [1]. However, the leakage current is considerably high due to the trap density of grain boundary [2]. It is well known that leakage current is originated from the electron-hole generation stimulated by electric field via trap-state on the grain boundary. Most previously reported structures, such as LDD (Lightly Doped Drain), undoped offset, successfully reduce the leakage current of poly-Si TFTs by the reduction of the electric field in the depletion region near the drain. However, in those device structures, the on current is also decreased due to high resistive region of LDD or undoped offset so that on/off current ratio is decreased [3, 4]. The purpose of our work is to propose and fabricate a new poly-Si TFT structure with selectively doped region between source and drain in order to improve the on/off current characteristics simultaneously. In the proposed poly-Si TFT, we employ the selectively doped regions in the active layer by an ion implantation as well as ion shower and the doping concentration of implanted ions is identical to that of source/drain.
Q9.11.1
DEVICE STRUCTURE AND EXPERIMENT The proposed poly-Si TFT has the selectively doped regions with in the active layer as shown in Figure.1. The selectively doped regions are orderly located and their doping concentration is identical to source/drain because ion-implantat
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