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0989-A20-04

Hot-Wire Deposited Nanocrystalline Silicon TFTs on Plastic Substrates Farhad Taghibakhsh, Michael M. Adachi, and Karim S. Karim School of Engineering Science, Simon Fraser University, 8888 University Drive, Burnaby, V5A 1S6, Canada

ABSTRACT Hot-wire chemical vapor deposition (HWCVD) was used to deposit nanocrystalline silicon (nc-Si) thin film transistors (TFT) on thin polyimide sheets. Two straight tantalum filaments at 1850°C with a substrate to filament distance of 4 cm was used to deposit HWCVD nc-Si with no thermal damage to plastic sheet. Top-gate staggered TFTs were fabricated at 150 °C and 250 °C using a HWCVD nc-Si channel, PECVD silicon nitride gate dielectric, and microcrystalline n+ drain/source contacts. A Leakage current of 3.3×10-12 A, switching current ratio of 3×106, and sub threshold swing of 0.51 V/decade were obtained for TFTs with aspect ratio of 1400 µm / 100 µm fabricated at 150 °C. The highest electron field effect mobility was found to be 0.3 cm2/Vs observed for TFTs deposited at lower substrate temperature. Measurements showed superior threshold voltage stability of HW nc-Si TFTs over their amorphous silicon (a-Si) counterparts.

INTRODUCTION Rugged plastic sheets can provide lightweight inexpensive substrates for large area thin film displays. Hot-wire chemical vapor deposition (HWCVD) technology is gaining popularity for depositing high quality materials because of its efficient use of source gases, and its simple and inexpensive setup which is easily scaleable for large area applications [1, 2]. Lack of ion bombardment and powder formation during deposition are the other advantages of the HWCVD technique. HWCVD is a physical deposition process, and unlike plasma enhanced deposition (PECVD) technique, a HWCVD system is entirely independent of the substrate (substrate does not need to be electrically grounded) which is a major advantage especially in roll-to-roll deposition systems for plastic sheets. However, adapting HWCVD for deposition on plastic substrates is a challenge due to the low temperature requirement of plastic substrates. Compared to state-of-the-art hydrogenated amorphous silicon thin film transistors (a-Si TFTs), nanocrystalline silicon (nc-Si) TFTs offer superior threshold voltage stability, as well as higher carrier mobility for both electrons and holes [3], providing the possibility of realizing an electronic system on plastic using thin film complementary metal oxide semiconductor (CMOS) transistors. The structure of the transistors plays an important role in performance of nonocrystalline devices. Because of conical growth of crystallites in a nc-Si thin film, top gate structures show better performance than bottom gate configurations due to higher

crystallinity of silicon film at the top of the layer. Also, the formation of an incubation bottom layer, which is amorphous, increases drain/source access resistance, and reduces the effective carrier mobility for top gate staggered TFT structures. This problem can be avoided in coplanar top gate configurat