Hybrid CMOS/memristor crossbar structure for implementing hopfield neural network
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Hybrid CMOS/memristor crossbar structure for implementing hopfield neural network Mahdiyar Molahasani Majdabadi1 • Jafar Shamsi1 • Shahriar Baradaran Shokouhi1 Received: 22 October 2018 / Revised: 16 August 2020 / Accepted: 24 September 2020 Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Competent hardware implementation of artificial neural networks is still an important contest. In recent literature, memristor has been introduced as a promising candidate for synapses implementation. However, integrating a memristive circuit with neuron hardware is auspicious research with challenging issues. In this paper, a scalable circuit-level hybrid CMOS/memristor hardware is introduced for implementing a Hopfield neural network. The proposed circuit is fully compatible with the crossbar structure. The performance of the proposed hardware is evaluated for different scales and compared with its software-based counterpart. Moreover, the accuracy of large-scale hardware for Hopfield neural network with 45 neurons and 4320 memristors is evaluated. It is demonstrated that the performance of the circuit is in the line of the software simulation. In comparison with similar works, the proposed circuit consumes 2000 times less energy and retrieves patterns 130 times faster. The implemented circuit is a step toward a general and feasible memristive hardware implementation for recurrent neural networks. Keywords Hopfield neural network Neural network hardware Memristor crossbar array Synaptic weights Hybrid CMOS/memristor circuit
1 Introduction Neuromorphic computing is an emerging field that utilizes VLSI technology to implement brain-inspired architectures such as Artificial Neural Networks (ANNs). Different architectures of ANNs have been introduced and exploited in a variety of applications [1–5]. A notable ANN is the Hopfield Neural Network (HNN), which is broadly used as an associative memory [6–9]. Since the introduction of HNN, its hardware implementation has been at the center of attention [10]. Designing a synaptic circuit is one of the most significant challenges in the hardware implementation of all ANNs, including HNN [11]. Several studies introduce different schemes to resolve the multi-aspect issue of the synaptic circuit design. The passive and active components are used to implement the synaptic circuits such as resistors [12], capacitors [13], and & Shahriar Baradaran Shokouhi [email protected] 1
School of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran
floating gates [14]. However, all of these methods have disadvantages. Using the resistor reduces the flexibility of the circuit. The capacitor requires some additional circuits to tackle the leakage current problem. Although the floating gate has an important role in the progress of neuromorphic computing, its power consumption and area overhead are the drawbacks [11, 15]. Since the invention of the memristor [16], this element has been considered as a promising candidate for designing synap
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