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Image and Video Capture Definition Image video capture interface is responsible for acquiring both data and control signals from the CMOS or CCD camera sensor as well as providing the appropriate formatting of the data prior to being routed to memory through DMA. The camera sensor may provide either raw or preprocessed image data to the interface through a variety of programmable options. The interface receives the video/image data stream from the camera sensor and provides all control signaling for this operation as either a Master or Slave device. In the Master mode, the line and frame synchronization signals are provided by the CMOS sensor and in Slave mode, the synchronization signals are provided by the interface (see Fig. 1). Several reduced pin-count alternatives are supported as subsets of the Master mode of operation. These include allowing the data to be serialized and the elimination of the separate synchronization signals for sensors that utilize the ITU-R BT.656 Start-ofActive-Video (SAV) and End-of-Active-Video (EAV) embedded in the data stream. The width of the data bus is also flexible and may be configured in an 8, 9, or 10- wire parallel mode or in a 4 or 5-wire serialized mode. The pixel data received may be in several possible formats. These formats include RAW, YCbCr 4:2:2, RGB 8:8:8, RGB 6:6:6, RGB 5:6:5, RGBT 5:5:5, and RGB 4:4:4. When a RAW capture mode is enabled, the data may be in 8, 9, or 10-bit formats. The RAW data is de-serialized if necessary, and then packed as

either 8-bit or 16-bit elements prior to transfer to memory. In a similar manner the pre-processed RGB and YCbCr image formats are packed into 16-bit or 32-bit elements. The YCbCr format has the additional option of being planerized prior to being stored to memory. This planarization facilitates SIMD processing (for example, using Wireless MMX) as well as immediate display using the color space conversion engine available in some advanced the LCD controller. The RGB formats may also be formatted to enable immediate preview using the LCD controller. Programmable options are provided to reduce RGB component

System bus DMA controller

Channel 2 Cr output FIFO

Channel 2 Cr output FIFO

Channel 0 Y or RGB output FIFO

Master control

CLK divider

Data packing

Slave control

SAV/EAV detect

Serial to parallel

Sensor interface Sync. signals

Pixel data bus

Image and Video Capture. Figure 1. Interface for image and video capture.

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Image and Video Quality Assessment

precisions and provide the transparency management for use with the LCD overlays. The formatting options offer value in reducing power consumption during the digital viewfinder preview sequence for image and video capture. For the camera sensors with higher pixel counts, only support raw format in favor of reducing camera complexity. Raw pixel processing (i.e., conversion from bayer pattern, correcting for noise and camera irregularities) can be done on the camera interface. Some advanced camera interfaces support these algorithmic operations.

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