Impact of aspect ratio of nanoscale hybrid p-Ge/n-Si complementary FinFETs on the logic performance
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TECHNICAL PAPER
Impact of aspect ratio of nanoscale hybrid p-Ge/n-Si complementary FinFETs on the logic performance Kallolini Banerjee1,2 • Suchismita Tewari2 • Abhijit Biswas2
Received: 30 August 2017 / Accepted: 8 November 2017 Ó Springer-Verlag GmbH Germany, part of Springer Nature 2017
Abstract We investigate the effect of aspect ratio (AR) with a given fin width (Wfin) of hybrid FinFETs at channel length of 20 nm on their digital performance using extensive numerical device and circuit simulations. The hybrid complementary FinFETs (HCFF), consist of Si channel n-FinFETs and Ge channel p-FinFETs and the performance is gauged in terms of device gain, noise margins (NMs), rise time (tr), fall time (tf) and propagation delay (td). Our findings reveal that tr and NM for our proposed HCFF inverter exhibit significant improvements of 37.31 and 8.03% compared to its corresponding Si value at aspect ratio of 5. Furthermore, the frequency of oscillations (fosc) of a nine-stage ring oscillator built using HCFF inverters shows 95.17% improvement with respect to that obtained with its equivalent Si counterpart at AR = 5 and supply voltage = 0.5 V.
1 Introduction During the last few decades, enhanced device performance has been achieved due to the aggressive miniaturization of Si CMOS devices. However, such extremely scaled devices have reached fundamental and technological limitations. Hence the semiconductor industry has been in search of & Suchismita Tewari [email protected] 1
Department of Electronics and Communication Engineering, University of Engineering and Management, University Area, Plot No. III-B/5, New Town, Action Area-III, Kolkata 700160, India
2
Institute of Radio Physics and Electronics, University of Calcutta, 92 Acharya Prafulla Chandra Road, Kolkata 700009, India
alternate channel materials along with the innovative device structures to alleviate these shortcomings. Relentless scaling down of device dimensions results in severe short channel effects (SCEs) (Tsormpatzoglou et al. 2007; Chaudhry and Kumar 2004). One of the most important SCEs is drain-induced-barrier-lowering (DIBL), which takes place particularly in an aggressively scaled device due to the lowering of source-channel barrier height on application of a high drain voltage. In order to mitigate SCEs, and to increase the gate control over the channel, the Tri-gate structure, commonly known as the FinFET architecture has been evolved as one of the viable choices due to its excellent scalability, electrostatic integrity, and process compatibility (Martin and Oruklu 2014). FinFET refers to a transistor architecture that utilizes a thin vertical film of semiconductor channel, called ‘‘Fin’’ from the source to drain. The portion of the Fin under the gate constitutes the channel and the source and drain are formed on either side of the Fin channel that is wrapped and controlled by the gate from three sides (Huang et al. 1999, 2001). The SCEs in the FinFET devices are effectively controlled by increasing the gate control over the chann
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