Impact of source-doping gradient in terms of lateral straggle on the performance of germanium epitaxial layer double-gat
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Impact of source‑doping gradient in terms of lateral straggle on the performance of germanium epitaxial layer double‑gate TFET Radhe Gobinda Debnath1 · Srimanta Baishya1 Received: 2 July 2020 / Accepted: 16 October 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract The impact of source doping gradient (SDG) in terms of lateral straggle (σ) on the performance of germanium epitaxial layer double-gate tunnel field effect transistor (ETL-DGTFET) was demonstrated by a simulation study. The non-zero tilt angle used in the ion implantation during the device fabrication process extends the implanted dopant atoms to the channel region from the source and drain which affects the performance of a device during both the ON- and OFF-states. To get a deeper insight of the impact of σ on the device performance, various DC performance parameters like Ion/Ioff ratio, average Subthreshold Slope (SSavg), and analog/RF figure of merits (FOMs) like transconductance (gm), output conductance (gds), intrinsic gain (gm/gds), parasitic capacitances and cutoff frequency (fT) were explored for σ variation from 0 to 5 nm. Circuit-level performance was also studied using an n-type ETL-DGTFET based resistive load inverter. Though the device performance is effected by the strain due to lattice mismatch between Si/Ge, it does not influence the effect of lateral straggle. Keywords DGTFET · Doping gradient · Gaussian doping · Lateral straggle · Epitaxial layer · BTBT
1 Introduction Tunnel field effect transistor (TFET) family of device has the capability to overcome the subthreshold slope limit of MOSFET, which can produce sub-60 mV/decade subthreshold slope [1, 2]. Due to the Band-to-band tunneling (BTBT), TFET gained the researcher’s attention [3]. Extensive research has been carried on/going on to improve the device performance as a steep slope switching device [4–9]. TFET with an epitaxial layer (ETLTFET), where the vertical tunneling (parallel to the gate electric field) takes place from source to ETL region shows an enhanced device performance as compared with conventional TFET [10]. Analysis of the ETLTFET up to now is mainly focused on the geometry and materials, including ideal conditions like uniform doping of the device [11, 12]. But in the fabrication process, the scenario is different from the ideal case. To precisely control the amount of implanted dopant atoms, the ion implantation technique is used in the fabrication process [13]. The non-zero tilt angle used in the ion implantation * Radhe Gobinda Debnath [email protected] 1
is an important factor in deciding the quality of abruptness at the junctions. This non-zero tilt angle extends the implanted dopant atoms into the channel region from the drain and source regions [14]. This worsens the abruptness of the source/drain junctions, which affects the performance of the device during both the ON- and OFF-states. Due to the extension of source and drain into the channel, the effective channel length decreases which improve the on current (Ion) an
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