Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circui
New variability resilient device architectures will be required at the 22 nm CMOS technology node and beyond due to the ever-increasing statistical variability in traditional bulk MOSFETs. A TCAD-based Preliminary Design Kit (PDK) development strategy is
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Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circuit Simulation A. Asenov, B. Cheng, A.R. Brown, and X. Wang
Abstract New variability resilient device architectures will be required at the 22 nm CMOS technology node and beyond due to the ever-increasing statistical variability in traditional bulk MOSFETs. A TCAD-based Preliminary Design Kit (PDK) development strategy is present here for a 10 nm SOI FinFET technology, with reliable device statistical variability coming from the comprehensive 3D statistical device simulation and accurate statistical compact modelling. Results from the statistical simulation of a 6T SRAM cell demonstrate the advantages of FinFET technology.
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Introduction
For over three decades, the progressive scaling of bulk CMOS transistors to achieve faster devices and higher circuit density has fuelled the phenomenal success of the semiconductor industry – captured by Moore’s famous law [1]. However, with the bulk device feature size reaching decananometre scales, the ever-increasing statistical variability in the device characteristics, introduced by discreteness of charge and granularity of matter, is becoming the major roadblock in the path of traditional bulk CMOS technology scaling. The standard deviation of the threshold
A. Asenov (*) • B. Cheng Department of Electronics and Electrical Engineering, Device Modelling Group, School of Engineering, University of Glasgow, Glasgow G12 8LT, UK Gold Standard Simulations Ltd, Rankine Building, Glasgow G12 8LT, UK e-mail: [email protected] A.R. Brown Gold Standard Simulations Ltd, Rankine Building, Glasgow G12 8LT, UK X. Wang Department of Electronics and Electrical Engineering, Device Modelling Group, School of Engineering, University of Glasgow, Glasgow G12 8LT, UK A.H.M. van Roermund et al. (eds.), Nyquist AD Converters, Sensor Interfaces, 281 and Robustness: Advances in Analog Circuit Design, 2012, DOI 10.1007/978-1-4614-4587-6_15, # Springer Science+Business Media New York 2013
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voltage distribution in minimum-sized square bulk nMOSFETs corresponding to a 45 nm low-power technology generation can exceed 50 mV, with the main contribution coming from random discrete dopants (RDD) in the channel region [2]. New variability-resilient device architectures, such as FinFETs and ultra thin body (UTB) SOI devices, will be required in order to maintain the benefits of technology scaling at the 22 nm node and beyond. Intel has introduced FinFET technology at the 22 nm high-performance technology node [3], and STMicroelectronics has already demonstrated the UTB SOI technology at the 28 nm technology node [4]. From a circuit and system designer’s point-of-view, without a reliable preliminary design kit (PDK) at the early stage of technology development, the introduction of new device architectures at the upcoming advanced technology nodes will bring the general design community into unchartered waters. Before the actual silicon data becomes available,
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