Implementation Aspects and Testbeds for MIMO Systems
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Editorial Implementation Aspects and Testbeds for MIMO Systems Thomas Kaiser,1 Andre´ Bourdoux,2 Markus Rupp,3 and Ulrich Heute4 1 Department
of Communication Systems, Faculty of Engineering, University of Duisburg-Essen, 47048 Duisburg, Germany vzw, DESICS Division, Kapeldreef 75, 3001 Leuven, Belgium 3 Institute of Communications and RF Engineering, TU Wien, Gusshausstrasse 25/389, 1040 Wien, Austria 4 Institute for Circuits and Systems Theory, Faculty of Engineering, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel-Gaarden, Germany 2 IMEC
Received 21 September 2005; Accepted 21 September 2005 Copyright © 2006 Thomas Kaiser et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
The MIMO (multiple-input multiple-output) systems have emerged as a key technology for wireless local area networks (WLANs), wireless metropolitan area networks (WMANs), and cellular mobile communication systems (3G, 4G) because they promise greater coverage, higher data rates, and improved link robustness by adding a spatial dimension to the time, the frequency, and the code dimensions. Recent progress in standardization and in first MIMO prototype chipsets has forced manufacturers worldwide to pay more attention to MIMO implementation aspects. Moreover, MIMO testbeds have become more and more attractive to universities and to research institutes as has been observed in the past few years. The aim of this special issue is to reflect the current state-of-the-art MIMO testbeds and to examine the several MIMO implementation challenges for current and for future wireless communication standards. We classified the accepted thirteen submissions into four major categories: (1) hardware-oriented prototypes, (2) flexible testbeds, (3) analog issues, and (4) fast algorithms. Hardware-oriented prototypes In the first paper, Guo et al. present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink, reducing the direct matrix inverse (DMI) to some FFT operations. Further parallel and pipelined VLSI architectures with Hermitian optimization and reducedstate FFT reduce the complexity even more. A comparative study of both the conjugate-gradient and the DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining
with a Catapult C high-level synthesis methodology. In the next paper, Dowle et al. describe the development of the STAR (space-time array research) platform, an FPGA-based research unit operating at 2.45 GHz and capable of having a maximum of twelve 20 MHz bandwidth channels of realtime, space-time, and MIMO processing. The design method starts with Matlab/Octave. With manual refinement steps, VHDL code for FPGAs is obtained and verified via ModelSim with the original design. Various pitfalls associated with the
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