Implementation of a high-throughput low-latency polyphase channelizer on GPUs
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Implementation of a high-throughput low-latency polyphase channelizer on GPUs Scott C Kim* and Shuvra S Bhattacharyya
Abstract A channelizer is used to separate users or channels in communication systems. A polyphase channelizer is a type of channelizer that uses polyphase filtering to filter, downsample, and downconvert simultaneously. With graphics processing unit (GPU) technology, we propose a novel GPU-based polyphase channelizer architecture that delivers high throughput. This architecture has advantages of providing reduced complexity and optimized parallel processing of many channels, while being configurable via software. This makes our approach and implementation particularly attractive for using GPUs as DSP accelerators for communication systems. Keywords: DSP accelerator; GPU front-end receiver; GPU-based radio; Polyphase filter; Polyphase channelizer
1 Introduction A modern communication transceiver contains two major components: a radio frequency integrated circuit (RFIC) and a baseband processor. An RFIC is responsible for conversion between analog and digital domain signals, and mixing signals up and down from baseband (BB) to some RF. A BB processor or a modem is responsible for handling all of the signal processing tasks and communication protocols. The notion of software radio (SWR) is defined in [1]. An SWR is responsible for the entire processing chain between RF and BB via software. In SWR systems, signal processing (SP) tasks, such as signal conversion, mixing, resampling, and filtering, are all done in BB using software in the discrete-time sample domain. An RFIC is then responsible for direct conversion to and from RF. A majority of the transceiver functionality is contained in the software modem. The goal of the software-based transceiver is to bring the SP functionality closer to the antenna as much as possible, reducing the burden on the RF front-end and utilizing the full flexibility of software. A software-based modem is particularly attractive over dedicated hardware solutions, such as ASIC- and FPGAbased solutions, due to significantly reduced design time from modeling to implementation to production. One of *Correspondence: [email protected] Department of Electrical & Computer Engineering, University of Maryland, College Park, MD 20742, USA
the major advantages of dedicated hardware is low-power design, but with the advancements made in system-onchip (SoC) architectures over the years with particular emphasis on low-power design, solutions based on programmable SoC architectures can deliver levels of energy efficiency that are sufficient for many applications (e.g., see [2]). An SoC can be delivered as a complete solution that integrates not only the radio unit but other key units, such as central processing unit (CPU), graphics processing unit (GPU), and peripheral controller subsystems, as well. A modern communication system requires multiple users and data streams to be processed simultaneously. A front-end transceiver must be able to transmit and receive
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