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Abstract The low temperature oxidation is effective for the atomically-controlled gate oxide growth. We focused the effects of post-oxidation annealing (POA) and attempted to improve the properties of the low-temperature-grown ultrathin oxides with a thickness of 3nm by POA. POA abruptly reduced the leakage current at a low gate voltage below 1.5V and the interface trap density. The correlation between the interface trap and the leakage current at a low applied voltage region were confirmed. We found that the stressing immunity of the ultrathin oxides grown at a low temperature, 650 0C, is drastically improved by POA at 850'C.

Introduction

Ultrathin gate oxides are required to be thinner than 3nm and to have a higher reliability than those of conventional oxides for sub 0.1[tm devices. The exact control of oxide thickness is essential because even a thickness deviation of one atomic layer results in over 10% of device parameter fluctuations. The low temperature oxidation is effective for the atomically-controlled gate oxide growth. We have been interested in SiO 2 films grown at a low temperature, and have been studying if they meet the requirement for sub 0.1[tm devices. Ultrathin SiO 2 films grown at low temperatures, however, have poor electrical properties possibly due to a large stress in the SiO 2 films at the Si/SiO 2 interface. It has been previously reported the post-oxidation annealing (POA) improves effectively the electrical properties of thin SiO 2 [1,2]. S.S.Cohen showed that oxides grown in an oxygen ambient, which are post-annealed for a long period of time in an inert atmosphere and then reoxidized for a short time, have considerably improved values for both the magnitude and distribution of the electric field at the dielectric breakdown [1]. In addition, Z.A.Weinberg et al. reported that short anneal in Ar or in N 2 can substantially reduce waterrelated electron traps and short anneal in 02 have an optimal time for hole trapping reduction [2]. 315 Mat. Res. Soc. Symp. Proc. Vol. 448 01997 Materials Research Society

Sample No. #650-1

Oxidation Temp=650°Cpure O2

N2

Annealing No

#650-2

Temp=650°Cpure 02

850°C,20min

#750-1

Temp=750°Cpure 02

No

#750-2

Temp=750°Cpure O2

750°C,20min

#750-3

Temp=750°Cpure O2

850°C,20min

#800-1

Temp=800°C,33% 02

No

#800-2

Temp=800°C,33% 02

800°C,20min

#800-3

Temp=800°C,33% 02

850°C,20min

#850-1

Temp=850°C,5% O2

No

#850-2

Temp=850°C,5% 02

850°C,20min

316

were measured using HP4145B Semiconductor Parameter Analyzer. The constant current density bias of -0.1A/cm2 was used for the charge-to-breakdown (Qbd) measurements. The constant voltage stressing for TDDB was performed at a room temperature. The interface properties were investigated from AC conductance method [3,4] using HP4284A LCR Meter because the influence of the DC-tunneling component can be separated.

Results and Discussion

I-V characteristics under a negative gate bias for each sample are shown in Figure 1. All I-V curves show that the leakage current due to the direct tunneli