Improving Stability of Pentacene Field-Effect Transistors with Post-Annealing
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1029-F09-12
Improving Stability of Pentacene Field-Effect Transistors with Post-Annealing Shun-Wei Liu1, Jia-Cing Huang2, Chih-Chien Lee2, Chin-Ti Lee1, and Juen-Kai Wang3,4 1 Institute of Chemistry, Academia Sinica, No. 128, Academia Rd., Taipei 11542, Taiwan, Taipei, Taiwan 2 Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, 106, Taiwan 3 Center for Condensed Matter Sciences, National Taiwan University, Taipei, 106, Taiwan 4 Institute of Atomic and Molecular Science, Academia Sinica, Taipei, 106, Taiwan ABSTRACT In this report, we demonstrate that the performance and stability of pentacene top-contact field-effect transistor can be greatly improved with post-annealing treatment. After postannealing at 90°C for 12 hours in nitrogen environment, the hole field-effect mobility of 0.3 cm2/Vs and the on/off current ratio of 107 were achieved, demonstrating 100% improvement in performance after the post-annealing treatment. The decay rate of drain current at constant gate and drain-source voltage was found to be decreased by more than 40%. The improved performance is attributed to the elimination of trapped holes and lattice defects in the organic semiconductor layer due to the post-annealing process. INTRODUCTION Organic field effect transistors (OFETs) have made impressive progress over the past ten years and its first electronic application are now beginning to appear [1]. Many groups have recently demonstrated integrated circuits, active-matrix displays, and chemical vapor sensors using organic semiconductors [2-4]. The device stability is one of the most critical issued in realizing these organic devices. Many degradation processes of organic semiconductors are related to oxygen- and moisture-associated species and can be minimized by adequate encapsulation. One of the appeared phenomena related to device reliability is the shift in the threshold voltage upon applying a bias to the gate electrode during device operation, so-called DC bias stress effects [5-6]. Such effect has also been observed in amorphous and polycrystalline-silicon-based transistors and is understood to originate from the deep trapping of conduction carriers [7-8]. The suppression of the DC bias stress effect is thus crucial to the reliable operation of organic transistors. In this letter, we present the dependence of this bias stress effect on post-annealing process. EXPERIMENT Pentacene FETs were fabricated on a heavily doped n-type Si wafer with a 300 nm thick thermally grown SiO2 layer (Cox = 11.5 nF/cm2). Prior to processing, the oxidized wafer was cleaned with a standard wet cleaning procedure, comprising ultrasonic cleaning in acetone and isopropanol. The 15-nm thin films of pentacene were grown by thermal deposition under 2×10-6 torr. During deposition, the substrate temperature was set at 80°C. Then, the source, drain and top Au electrodes of 50 nm thickness was deposited through a shadow mask on the middle-
contact type, and lateral dimensions were defined by shadow mask. The channel
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