Innovative Device Architecture for High Efficiency Thin Film Silicon Solar Cells
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Innovative Device Architecture for High Efficiency Thin Film Silicon Solar Cells Mathieu Boccard, Matthieu Despeisse, Christophe Ballif Ecole Polytechnique Fédérale de Lausanne (EPFL), Institute of Microengineering (IMT), Photovoltaics and Thin film Electronics Laboratory, Rue Bréguet 2, CH-2000 Neuchâtel, Switzerland ABSTRACT The challenge for all photovoltaic technologies is to maximize light absorption, convert photons with minimal losses to electrical charges and efficiently extract them towards the electrical circuit. For thin film silicon solar cells, a compromise must be found as light trapping is usually performed through textured interfaces, that are detrimental to the subsequent growth of dense and high quality silicon layers. We introduce here the concept of smoothening intermediate reflecting layers (IRL), enabling to combine high currents and good electrical quality in Micromorph devices in the superstrate configuration. After exposing the motivation for such structures, we validate the concept by showing a VOC enhancement when employing a polished silicon-oxide-based IRL. Shunting issues and additional reflection losses are pointed out with such technique, highlighting the need to develop alternative techniques for an efficient morphology adaptation before the microcrystalline silicon cell growth. INTRODUCTION By directly converting free, abundant and equally distributed sunlight to electricity, photovoltaics has a major role to play in tomorrow’s energy supply. For very large scale development, thin film silicon is the most favorable technology thanks to its sparse use of abundant and non-toxic material. However, the best efficiencies currently obtained under standard test conditions (around 14%) are still lower than that of historical wafer-based monocrystalline technology (up to 25%), in spite of a theoretical limit over 30% for the “Micromorph” tandem device consisting of an amorphous silicon / microcrystalline silicon (a-Si / μc-Si) top / bottom cell [1]. Better material quality (to obtain a better voltage output) as well as better light harvesting (for higher electrical current output) are both necessary to attain such high efficiency. Both are strongly interlinked, as the classical way of elongating the light path in the absorber layer is by texturing the substrate on which the silicon layers are grown [2-4], and whereas light management considerations acclaim rugged surface morphologies, the latters can trigger the formation of spatially inhomogeneous photoactive layer with local low quality areas [5-8]. Continuous effort is made to improve light trapping through advanced photonic structures, but the high cost on electrical cell parameters often results in reduced efficiency. We recently suggested in [8] a multiscale texturing architecture for the front electrode that enables excellent light trapping (as obtained with a state-of-the-art single-scale LPCVD ZnO layer) and simultaneously provides a suitable surface for the growth of high quality silicon layers. In this approach, a smooth and large
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