Interleaved Convolutional Code and Its Viterbi Decoder Architecture
- PDF / 690,810 Bytes
- 7 Pages / 600 x 792 pts Page_size
- 17 Downloads / 181 Views
Interleaved Convolutional Code and Its Viterbi Decoder Architecture Jun Jin Kong Department of Electrical and Computer Engineering, University of Minnesota, 200 Union Street, Minneapolis, MN 55455, USA Email: [email protected]
Keshab K. Parhi Department of Electrical and Computer Engineering, University of Minnesota, 200 Union Street, Minneapolis, MN 55455, USA Email: [email protected] Received 4 February 2003 and in revised form 17 June 2003 We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code. The state-parallel architecture uses as many add-compare-select (ACS) units as the number of trellis states. By replacing each delay (or storage) element in state metrics memory (or path metrics memory) and path memory (or survival memory) with I delays, interleaved Viterbi decoder is obtained where I is the interleaving degree. The decoding speed of this decoder architecture is as fast as the operating clock speed. The latency of proposed interleaved Viterbi decoder is “decoding depth (DD) × interleaving degree (I) + extra delays (A),” which increases linearly with the interleaving degree I. Keywords and phrases: interleaved convolutional code, interleaved Viterbi decoder, burst-error correction, random-error correction, interleaving.
1.
INTRODUCTION
It is well known that burst-error is a serious problem especially in storage and wireless mobile communication systems. In order to cope with burst-error, interleaving, denoted here as channel interleaving, with random-error correcting code, is generally used. Interleaving randomizes error bursts by spreading the erroneous bits with introducing a very long delay time, which is intolerable in some applications. A burst-error correcting Viterbi algorithm, which combines maximum likelihood decoding algorithm with a burst detection scheme, instead of using channel interleaving, was proposed in [1] and extended to the Q2 PSK in [2]. This adaptive Viterbi algorithm (AVA) outperforms interleaving strategies in the presence of very long bursts. However, when many short error bursts are present, AVA is inferior to interleaving scheme. An interleaved convolutional code also can be used for burst-error correction [3]. A modified Viterbi algorithm (MVA) [4], which is based on the multitrellis decomposition [5], was presented for interleaved convolutional code. The MVA introduces a much smaller delay time and much lower memory requirements than channel interleaving techniques with convolutional code. However, the implementation of MVA in [4], which uses as many delay elements as decoding depth (DD) × interleaving degree (I) for
each code word component, is not area efficient. Some applications of interleaved convolutional code for asynchronous transfer mode (ATM) networks [6] and image communication systems [7, 8, 9] have been proposed. In this paper, an area-efficient high-speed interleaved Viterbi decoder architecture, which has sta
Data Loading...
