Introduction to On-Chip Interconnects and Modeling
This chapter briefs about the challenges associated with the modeling of on-chip interconnects in nanoscale technology. Copper had been used as an on-chip interconnect material for a long time. However, as device dimensions are scale down the reliability
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Introduction to On-Chip Interconnects and Modeling
Abstract This chapter briefs about the challenges associated with the modeling of on-chip interconnects in nanoscale technology. Copper had been used as an on-chip interconnect material for a long time. However, as device dimensions are scale down the reliability decreases due to electromigration induced problems. Therefore, researchers are forced to find an alternative solution for future high-speed global VLSI interconnects. This chapter introduces the evolution of graphene interconnect materials and the challenges associated with them. This chapter also introduces the FDTD technique for the modeling of on-chip interconnects.
Keywords Carbon nanotube (CNT) Copper Finite-difference time-domain (FDTD) Graphene nanoribbon (GNR) Interconnects Very large scale integration (VLSI)
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Introduction
Advancement of technology in the nanometer regime considers high-speed and high-density very large scale integration (VLSI) circuits. It is desirable to use multilayer interconnections in three or more levels to achieve higher packing densities and smaller footprint [1, 2]. Based on the length and cross-sectional dimensions, the on-chip interconnects can be broadly characterized into three categories: local, intermediate, and global interconnects. Local interconnects consist of very thin lines, used to connect gates and transistors in a functional block. Intermediate interconnects are wider and longer than local interconnects, provide low-resistance signal paths in a functional block. The global interconnects provide long-distance communication between the functional blocks and have a large cross-sectional area to minimize the resistance [3]. The global interconnects are placed at the higher level of the chip and can be as long as 1–2 cm in current high-performance integrated circuits [1]. In early days, the operating speed of an integrated circuit was limited by the speed of a logic gate. Interconnects between the gates were considered as ideal © The Author(s) 2016 B.K. Kaushik et al., Crosstalk in Modern On-Chip Interconnects, SpringerBriefs in Applied Sciences and Technology, DOI 10.1007/978-981-10-0800-9_1
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1 Introduction to On-Chip Interconnects and Modeling
conductors, where the signal propagates instantaneously. Therefore, the interconnects had little effect on circuit operation. However, after the introduction of submicron semiconductor devices, the ideal behavior of interconnects no longer remains adequate. In fact, the performance of the chip is primarily determined by the interconnect line rather than the device [4]. At high operating frequencies, the closely packed interconnects produce transient crosstalk [5–7]. The undesired effect created on one line due to a signal transmitted on another line is defined as crosstalk. The crosstalk noise strongly influences the signal propagation delay and causes the circuit malfunction or functional failure. Based on the switching transitions in the coupled lines, crosstalk can be broadly classified int
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