Investigation of interface trap charges and temperature variation in heterostacked-TFET
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ORIGINAL PAPER
Investigation of interface trap charges and temperature variation in heterostacked-TFET K Vanlalawmpuia*
and B Bhowmick
Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam 788010, India Received: 31 July 2019 / Accepted: 06 March 2020
Abstract: This paper analyzes the reliability issues of the Heterostacked-TFET (HS-TFET) in detail. The investigation of the device reliability is carried out by examining the effect of interface trap charges (ITCs) and the temperature affectability of the HS-TFET on various analog parameters and RF FOMs. The analysis is performed at different interface trap charge densities and polarities. The presence of interface traps at the stackedsource/channel junction and the oxide/ silicon interface alters the performance of the device significantly. A positive trap charge density of 3 9 1013 cm-2 degrades the current switching ratio tremendously from an order of 1010–104. The off-state current of the device deteriorates excessively at high temperatures. However, the results establish that the HS-TFET is insusceptible to the acceptor interface trap charge as compared to the donor interface trap charge for temperature variation. A high-k gate dielectric of Aluminum oxide (Al2O3) is considered and compared with Hafnium oxide (HfO2) and it is found that Al2O3 gate oxide has a better immunity to the ITC variation. Keywords: Heterostacked; Band-to-band tunneling; Tunnel FET; Interface trap charges; Temperature affectability PACS Nos.: 61.72.Tt; 61.82.Fk; 73.40.Gk; 73.40.Qv; 85.30.-z
1. Introduction Over the past decades, the complementary metal–oxide– semiconductor (CMOS) technology has revolutionized the semiconductor industries in many ways and has become the main technological driver for low-power applications [1]. However, continuous downscaling of CMOS has led to several problems, such as high subthreshold swing (SS), hot carrier effects, high leakage current and other shortchannel effects (SCEs) [2–4]. Due to these issues, several novel devices have been explored that rely on a new operation mechanism rather than the thermionic emission on the potential barrier as in the case of the metal–oxide– semiconductor field-effect transistor (MOSFET). The tunnel field-effect transistor (TFET) is anticipated as a promising candidate to overcome the subthreshold swing fundamental limit of 60 mV/decade at room temperature and high leakage off-current of the MOSFET as TFET operates on tunneling mechanism between the interband at
the source/channel [5–9]. Apart from the low leakage off current and the sub-kT/q SS, TFET also offers negligible amount of SCEs, significant enhancement in the current ratio (ION/IOFF) and the gain [10]. Due to these exquisite characteristics, TFETs have acquired tremendous attention in both analog and RF applications. However, regardless of all these advantages, conventional TFET endures from substantially low ON currents (ION), high threshold voltage (Vth), ambipolar currents and high average su
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