Investigation of NBTI Recovery During Measurement
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0917-E03-02
Investigation of NBTI Recovery During Measurement Robert Entner1, Tibor Grasser1, Hubert Enichlmair2, and Rainer Minixhofer2 1 TU Wien, Christian Doppler Laboratory for TCAD in Microelectronics, Gusshausstrasse 2729/E360, Vienna, 1040, Austria 2 Austriamicrosystems, Unterpremstaetten, 8141, Austria
ABSTRACT In this work we present a rigorous investigation of the negative bias temperature instability (NBTI) recovery process during measurement intervals in comparison to the numerical solution of an extended reaction-diffusion (RD) model. In contrast to previous work, the RD model has been implemented in a multi-dimensional device simulator and is solved selfconsistently together with the semiconductor device equations. This allows us to directly use many commonly approximated quantities such as the oxide electric field and the interface hole concentration in a self-consistent manner. In addition, the influence of the trapped charges can be more accurately considered by using a distributed Shockley-Read-Hall interface trap-charge model [1, 2] which has been coupled to the RD model. Thus, due to the self-consistent solution procedure, also the feedback of these charged interface-states on the Poisson equation is considered which influences the observed threshold voltage shift. Experimental data confirm the model which has been calibrated to a wide range of temperatures using a single set of parameters. INTRODUCTION Negative bias temperature instability (NBTI) has come to the forefront of not only academic but also industrial interest. It occurs in p-type MOS devices stressed with negative gate bias at elevated temperatures. In particular for thicker oxides, as used in high-voltage devices, the degradation can be ascribed to two major effects, the generation of interface traps Nit at the Si/SiO2 interface and the generation of fixed oxide charges in the dielectric. These effects lead to a shift of important transistor parameters such as the threshold voltage Vth, the drain current ID, the transconductance gm, and the off current Ioff. The degradation can cause timing shifts of logic circuits and thus lead to circuit failure. Due to the need for accurate prediction of device and circuit lifetimes, modeling and simulation of the degradation physics has gained importance. There are two important factors for accurate modeling: (a) the physics of the degradation mechanisms have to be modeled as precisely as possible (b) the experimental and measurement setup must lead to an exact description of the device state. Here, especially the applied measurement technique needs special attention, as the method used for evaluating NBTI degradation can have a considerable impact on life-time extrapolation results [14, 4].
THE ORIGINAL MODEL Our model is an enhanced version of the original work by Jeppson and Svennson [5]. Their proposed reaction-diffusion (RD) model describes the degradation process as a reaction at the Si/SiO2 interface generating a positively charged interface state (Nit) as well as releasing a mobile h
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