Investigation of Pt/Si/CeO 2 /Pt MOS Device Structure by Impedance Spectroscopy
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Investigation of Pt/Si/CeO2/Pt MOS Device Structure by Impedance Spectroscopy Jyrki Lappalainen1, Darja Kek2, and Harry L. Tuller Crystal Physics and Electroceramics Laboratory, Department of Materials Science and Engineering, MIT, 77 Massachusetts Avenue, Cambridge, MA 02139, USA
ABSTRACT Epitaxial growth of dielectric layers on silicon substrates has attracted a great deal of recent interest given their potential applicability in the fabrication of high quality silicon-on-insulator (SOI) structures, high density capacitor devices, and stable buffer layers between silicon and other materials. Cerium dioxide (CeO2) appears to be a particularly attractive candidate, given its high dielectric constant and its compatibility with Si. To date, measurements of the electrical properties of CeO2 films on Si have been largely limited to room temperature. In this study, thin films of CeO2 were prepared by in situ pulsed laser deposition (PLD) on n-type (100) silicon substrates, with varied deposition conditions. Capacitance-voltage measurements (C-V) were used to characterize the response of the Pt/Si/CeO2/Pt MOS capacitor structure. Impedance measurements were performed from room temperature to 350 °C. This enabled the independent characterization of the electrical signature of the Pt/Si interface which was found to contribute insignificantly above approximately 150 °C. The CeO2 film conductivity was found to be thermally activated with activation energy of ~0.45 eV, with its magnitude strongly dependent on film microstructure.
INTRODUCTION A rapidly converging interest in thin film oxides has been developing in the microelectronics and solid state ionics communities. The continued drive towards ever smaller submicron lateral dimensions in MOSFET technology has pushed SiO2 gate oxide thickness to the order of nanometers leading, in turn, to higher leakage currents and processing difficulties. Replacement of the SiO2 films by thicker films with higher dielectric constants compared to SiO2 (εr ≈ 3.5) promises equivalent capacitances with reduced leakage and threat of electrical breakdown [1]. In the solid state ionics arena, there is much interest in reducing the operating temperatures of solid state oxide fuel cells (SOFC) by shifting from bulk to thin film electrolytes (stabilized ZrO2 or acceptor doped CeO2). Indeed, the possibility thereby exists to embed miniaturized SOFC structures as power sources together with microelectromechanical (MEMS) components, and other active electronics into the same silicon wafer [2]. CeO2 is a particularly attractive oxide for integration onto silicon substrates. The lattice constant mismatch between diamond-structured silicon and fluorite-structured CeO2 is only about 0.35%. This enables the fabrication and deposition of stress free, highly oriented or epitaxial thin film structures using, for example, sputtering, electron beam evaporation, or pulsed laser deposition (PLD) techniques. Furthermore, CeO2 forms no undesirable compounds, like 1
Permanent address: Microelectronics Laboratory
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