Investigation of the Role of Chemical-Mechanical Polishing in Improving the Performance of Polysilicon TFTs
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INVESTIGATION OF THE ROLE OF CHEMICAL-MECHANICAL POLISHING IN IMPROVING THE PERFORMANCE OF POLYSILICON TFTs B. Lee, L.J. Quinn, P.T. Baine, S.J.N. Mitchell, B.M. Armstrong and H.S. Gamble Northern Ireland Semiconductor Research Centre, Dept. of Electrical and Electronic Engineering, Queen's University Belfast, United Kingdom ABSTRACT Polycrystalline silicon thin-film transistors (TFTs) have been fabricated on glass substrates using a low temperature top-gate self-aligned process. The interface between the polysilicon active layer and the silicon dioxide oxide gate dielectric is of vital importance in order to achieve good thin-film transistor electrical characteristics. Carrier transport takes place within l0nm of this interface, and any roughness in this region, corresponding to the initial surface roughness of the polysilicon layer, causes scattering of the carriers and a higher density of interface traps. Chemical-mechanical polishing has been used to reduce the initial surface roughness of the polysilicon. Electrical parameters of polished TFTs, such as mobility and threshold voltage, show a marked improvement compared to unpolished devices. INTRODUCTION Polycrystalline silicon thin film transistors (TFTs) have attracted much attention due to their applications in active matrix liquid crystal displays [1]. Since these films are deposited on glass, it is essential that a high quality process can be developed at low temperatures (_
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