Investigation on different organic semiconductor/organic dielectric interfaces in pentacene-based thin-film transistors
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1029-F02-03
Investigation on different organic semiconductor/organic dielectric interfaces in pentacenebased thin-film transistors Emanuele Orgiu1,2, Mohammad Taki1, Beatrice Fraboni3, Simone Locci1,2, and Annalisa Bonfiglio1,2 1 DIEE, Department of Electrical and Electronic Engineering, University of Cagliari, piazza d'armi, Cagliari, 09123, Italy 2 INFM Centre S3 "nanoStructures and bioSystems at Surfaces", Modena, 41100, Italy 3 Department of Physics, University of Bologna, viale Berti Pichat 6/2, Bologna, 40127, Italy ABSTRACT Organic Thin-Film Transistors (OTFTs) in top-contact configuration and MetalInsulator-Semiconductor (MIS) structures with different organic dielectrics as the gate insulator have been fabricated using the same organic semiconductor layer, pentacene, in order to investigate the changes in the electrical behavior by varying the interface properties. A gold bottom gate electrode was sputtered on a glass substrate whereas gold source and drain were thermally evaporated onto the pentacene layer. Several organic dielectrics have been tested as insulating layers, namely poly(vinyl alcohol) (PVA), polyvinyl alcohol cross-linked with ammonium dichromate (c.l. PVA) poly (4-vinyl phenol) (PVP), poly(dimethylsiloxane) (PDMS) and poly(methylsilsesquioxane) (pMSSQ). The interesting differences found by varying the interface confirm that the chemical-physical interaction between semiconductor and dielectric is crucial for the conduction mechanisms of the charge carriers. INTRODUCTION The interface between an organic semiconductor and a dielectric plays a decisive role in the functional performance of Organic Thin-Film Transistors [1-6]. Since it is well-known that charge carriers flow through the channel in the first few nanometers, i.e. at the interface between the semiconducting and the insulating layer, a better understanding of the interface phenomena involved in the conduction mechanism is needed. In fact, designing an interface that promotes synergistic interactions between the semiconductor and the dielectric is essential in achieving optimum FET performance. It is widely recognized that the gate dielectric surface roughness is a key parameter that influences OTFT electrical performances [7] and it was shown that rougher gate dielectric surfaces result in smaller pentacene grains and lower OTFT carrier mobilities [8].On the other hand, comparative studies [4] of pentacene grown both on polyvinyl alcohol (PVA) and polyvinylphenol (PVP) have shown OFET comparable performance, despite the well-structured morphology of the pentacene film on PVP. In addition, recent studies [6] indicate that the ordering of pentacene molecules increases significantly on certain surfaces even if these surfaces have higher rms roughness than others. The hydroxyl groups of dielectric at the interface seem to be responsible for the trapping of electrons at the interface semiconductor/dielectric [5], thus suggesting that the use of an appropriate hydroxyl-free gate dielectric can yield n-channel FET conduction in most conj
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