IP Cores Design from Specifications to Production Modeling, Verifica
This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many
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Khaled Salah Mohamed
IP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protection
Analog Circuits and Signal Processing
Series editors Mohammed Ismail Mohamad Sawan
More information about this series at http://www.springer.com/series/7381
Khaled Salah Mohamed
IP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protection
Khaled Salah Mohamed Emulation Mentor Graphics Heliopolis, Egypt
ISSN 1872-082X ISSN 2197-1854 (electronic) Analog Circuits and Signal Processing ISBN 978-3-319-22034-5 ISBN 978-3-319-22035-2 (eBook) DOI 10.1007/978-3-319-22035-2 Library of Congress Control Number: 2015947256 Springer Cham Heidelberg New York Dordrecht London © Springer International Publishing Switzerland 2016 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper Springer International Publishing AG Switzerland is part of Springer Science+Business Media (www.springer.com)
Preface
This book discusses the life cycle process of IP cores from specification to production which includes four major steps: (1) IP modeling, (2) IP verification, (3) IP optimization, and (4) IP protection. Moreover, the book presents most of the famous memory cores and controller IPs and analyzes the trade-off between them. In this book, we give an in-depth introduction to SoC buses and peripheral IPs. We explain their features and architectures in detail. Moreover, we provide a deep introduction to Verilog from both implementation and verification points of view. The book presents a simple methodology in building a reusable RTL verification environment using UVM. UVM is a culmination of well-known ideas and best practices. Moreover, it presents simple steps to verify an IP and build an efficient and smart verification environment. A SoC case study is presented to compare traditional verification with a UVM-based verification. Bug localization is a process of identifying specific locations or regions of source code th
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