Leakage Currents through Thin Silicon Oxide Grown on Atomically Flat Silicon Surfaces
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Leakage Currents through Thin Silicon Oxide Grown on Atomically Flat Silicon Surfaces Valerian Ignatescu and Jack M. Blakely Materials Science & Engineering, Cornell University 214 Bard Hall, Ithaca, NY 14853–1501 ABSTRACT Atomically flat surfaces can be obtained by high-temperature annealing in UHV of specially patterned silicon samples. Thin silicon oxide layers were grown by dry oxidation on three types of surfaces: (a) atomically flat surfaces, (b) normal (stepped) surfaces cleaned in UHV by the same high-temperature annealing and (c) normal wafer surfaces, which underwent just an RCA chemical cleaning before oxidation. Atomic force microscopy (AFM) was performed to reveal the topography of the surfaces. Aluminum pads were deposited on these oxidized surfaces using photolithography techniques. The leakage current through the oxide was measured for all three cases. Our results show that the smoother the surface before oxidation, the smaller the leakage current. INTRODUCTION The decrease in channel length of transistors in order to achieve higher switching frequency has led to a corresponding oxide gate thickness almost at its physical limits: 1.2 nm silicon oxide for the current 90 nm process generation, or in other words, just about 5 silicon atoms across. Muller et al. [1] have shown that due to the finite width of the interface transition region between silicon and silicon oxide, the minimum thickness for the dielectric to retain its insulating properties is ~ 0.7 nm. But from the technological point of view, anything below 1 nm does not seem to be feasible [2]. The introduction of alternative, high-dielectric constant materials for the gate insulator will probably not occur until 2007, in the 45 nm process [3]. The surfaces of normal Si wafers deviate from their nominal orientation by about 0.5°. Due to this miscut angle, the structure of a wafer surface will consist of a succession of steps and terraces whose detailed configuration depends on the step density and the interactions among the steps. These atomic steps have an average height of ~ 0.3 nm for Si(111) so that they can cause significant variations in the effective thickness of ultra-thin SiO2 over-layers (or other dielectric gate materials) [4]. In our research we have focused on the control of the morphology of the starting Si surface and its effect on the morphologies of the oxide surface and Si-SiO2 interface. In this paper we report on the effect of atomic steps on the leakage current in MOS capacitors. SAMPLE PREPARATION Samples were prepared from boron-doped Si(111) wafers with a resistivity 0.7 – 0.8 Ω-cm. A sacrificial layer of silicon oxide was grown by wet oxidation or deposited by chemical vapor deposition. Using photolithography and dry etching, we created arrays of square craters (25x25 µm), about 800 nm deep. Samples with dimension of 18 x 7 mm were cut from the wafers,
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cleaned with HF, rinsed with di-ionized (DI) water and loaded in a UHV chamber where the pressure was maintained below 10 -10 torr. Obtaining atom
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