Low-Noise Low-Power Design for Phase-Locked Loops Multi-Phase High-P
This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for m
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Feng Zhao • Fa Foster Dai
Low-Noise Low-Power Design for Phase-Locked Loops Multi-Phase High-Performance Oscillators
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Feng Zhao Santa Clara California USA
Fa Foster Dai Department of Electrical and Computer En Auburn University Auburn Alabama USA
ISBN 978-3-319-12199-4 ISBN 978-3-319-12200-7 (eBook) DOI 10.1007/978-3-319-12200-7 Library of Congress Control Number: 2014954239 Springer Cham Heidelberg New York Dordrecht London © Springer International Publishing Switzerland 2015 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Preface
This book covers unique design techniques for phase-locked-loop (PLL) frequency synthesizers, including quantization noise reduction, low power design methodology for dividers, and high-performance multi-phase clock generation techniques. PLL is a critical building block for frequency synthesis in wired and wireless communication systems. This book first introduces fundamentals about fractional-N PLL design. It analyzes the quantization noise of ΣΔ modulator based fractional-N PLL. ΣΔ modulation is a commonly used technique for fractional spur reduction. However, quantization noise caused by ΣΔ modulator degrades the phase noise performance at the PLL output. The noise degradation becomes worse when the loop is nonlinear. In this book, noise reduction and cancellation techniques are presented to solve the problems associated with noise degradation due to ΣΔ modulation. Also analyzed is the impact of charge pump nonlinearity on phase noise performance. System-level behavioral model is developed for the analysis of charge pump nonlinearity. For low power PLL design, a wideband integer-N PLL with power optimized dividers is presented. An intuitive, yet efficient power optimization methodology is introduced for optimizing divider power consumptions using both bipolar and CMOS technologies. Quadrature signals are needed in image-rejection
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