Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes
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Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes Shahram Mohammadi 1 & Reza Omidi 1
&
Mohammad Lotfinejad 1
Received: 14 April 2020 / Accepted: 15 May 2020 # Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In this paper, we propose a low-power yet area-efficient fault tolerant adder by using Berger codes. The proposed Berger code checker is designed by using the current mode multi-valued logic (CM-MVL) circuits. The proposed structure, which is more area and power efficient than state-of-the-art fault tolerant adders, is able to detect all single and multi-bit unidirectional faults. The efficiency of the proposed fault tolerant adder is evaluated by comparing its characteristics to those of two state-of-the-art fault detection schemes in adders as well as the conventional duplex and parity bit checkers in a 90 nm technology. The results reveal that the proposed 64-bit Berger code checker for adders imposes up to 6.7% and 27.2% delay and area penalties, respectively with a cost of static power dissipation. In the proposed scheme, in sub threshold regime, the power penalty is just 1%, while its area overhead is only 31%. The drawback of using this scheme in sub threshold regime is that delay time introduced to the circuit is unacceptable. So, depending on the application, we should choose one of the above-mentioned schemes. Keywords Fault tolerant adder, Berger code checker, Current mode, Multi-valued logic
1 Introduction With the advancement and development of VLSI circuits by shrinking the device feature sizes, an increase in the number of faults is observed. This is because smaller technologies are more susceptible to defects and smaller particles like cosmic rays. So, as technology scales, fault tolerance is becoming a key concern especially in critical applications. This paper intends to propose an area-efficient checker circuit to detect faulty states in adders. In the proposed scheme, Berger codes are used to detect a faulty state. Although the theory of using Berger codes for adders has been already investigated, however an efficient and practical scheme has not been yet proposed. Berger code is a unidirectional error detecting code which is introduced by J. M. Berger [2]. This coding scheme is basically introduced and used in telecommunication, but later, it was used as error detection mechanism in the arithmetic circuits and other digital circuits [9, 10]. Responsible Editor: S. Hellebrand * Reza Omidi [email protected] 1
Electrical Engneering Department, Faculty of Engineering, University of Zanjan, Zanjan 45371-38791, Iran
Recently, a fault tolerant FIR filter using Berger codes [16, 18] and a Berger code based self-testing processors have been introduced in [1]. More details can be found in [1, 2, 9, 16]. In this paper, by using the simple current mirrors and a differential topology which are similar to current mode multi valued logic, a novel Berger code checker circuit is presented for “adders”. Multi valued logic (
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