Low Temperature Plasma Etching of Copper for Minimizing Size Effects in sub-100 nm Features
- PDF / 173,603 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 23 Downloads / 180 Views
0914-F09-08
Low Temperature Plasma Etching of Copper for Minimizing Size Effects in sub-100 nm Features Nagraj S Kulkarni1, Prabhakar Tamirisa2, Galit Levitin2, Richard J Kasica1, and Dennis W Hess2 1 Oak Ridge National Laboratory, Oak Ridge, TN, 37831 2 School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, 311 Ferst Drive, N.W., Atlanta, Georgia, 30332-0100 ABSTRACT A low temperature plasma etching process for patterning copper interconnects is proposed as a solution to the size effect issue in the resistivity of copper. Key features of this etching process based on a previous thermochemical analysis of the Cu-Cl-H system are discussed. Potential benefits of a subtractive etching scheme based on this process in comparison with the damascene scheme for copper-based interconnect processing in sub-100 nm features are presented in the context of the ITRS roadmap. Preliminary experimental work on plasma etching of Cu thin films using the proposed process is discussed.
INTRODUCTION Adherence to Moore’s Law projections for maintaining competitiveness in the semiconductor industry has placed stringent requirements on the density of interconnects used in devices manufactured using CMOS technology. In order to meet interconnect density targets, the number of metal layers, typically made of Al or Cu, increases while the interconnect dimensions decrease. The use of Cu over Al as the preferred choice of the conductive material has provided a significant reduction in the electrical resistivity (40%) and hence the RC constant, where R is the effective resistance and C the effective capacitance, while simultaneously improving the electromigration (EM) resistance (by 5X). Since Al-based metallization using a subtractive or reactive ion etching (RIE) process was not successful for Cu, IBM introduced the damascene technology for Cu metallization [1, 2], a process in which subtractive etching of Cu is avoided by electroplating Cu in etched dielectric structures followed by chemical mechanical planarization (CMP) of the overburden Cu layer deposited over the dielectric. While the transition to Cu using damascene technology was successfully implemented after several years of intensive effort, and helped in extending the validity of Moore’s Law to several generations of CMOS technology, a new and significant roadblock has appeared on the horizon for future generations, where feature dimensions less than 100 nm are needed. This roadblock is due to the “size effect” in Cu [3], a phenomenon in which the electrical resistivity of Cu increases significantly as the lateral dimensions are reduced to less than 100 nm and approach the electron mean free path of Cu (40 nm in Cu at 25oC). For a 50 nm narrow Cu wire needed in future generations of CMOS technology, the resistivity measured is roughly twice the bulk value of 1.7 µohm-cm [3, 4]. The size effect in the resistivity is critical to the semiconductor industry, since it increases the voltage drop and the signal propagation delay, and increases Joule heating in n
Data Loading...
