Low-temperature ultraviolet sol-gel photoannealing processing of multifunctional lead-titanate-based thin films
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. Guillon KEMSTREAM, Advanced Vaporizers, Rue de la vieille poste, PIT de la Pompignane, Batiment T2, 34055 Montpellier, Cedex 1, France
J. Ricote and L. Pardo Instituto Ciencia de Materiales de Madrid (CSIC), Cantoblanco, 28049–Madrid, Spain (Received 15 September 2006; accepted 7 February 2007)
(Pb1−xCax)TiO3 perovskite thin films with nominal compositions of (Pb0.76Ca.24)TiO3 (ferroelectric) and (Pb0.50Ca0.50)TiO3 (relaxor-ferroelectric) were prepared on silicon substrates at low temperatures compatible with those used in Si-technology. The technique used for the processing of these films was ultraviolet (UV) sol-gel photoannealing, using photo-sensitive precursor solutions and UV-assisted rapid thermal processing. The UV-irradiation and thermal treatment of the solution-derived films (gel films) were carried out in air or in oxygen. In both cases, the formation of the perovskite occurred at the same temperature, and this temperature increased as the Ca2+ content increased. Thus, full-perovskite films of (Pb0.76Ca.24)TiO3 were obtained at 723 K whereas those of (Pb0.50Ca0.50)TiO3 were formed at 773 K. Well-defined ferroelectric hysteresis loops were measured in the (Pb0.76Ca.24)TiO3 films, with values of remanent polarization of Pr ∼ 11 C cm−2 and coercive fields for the films processed in oxygen lower than those of the films processed in air, Ec ∼ 164 and ∼226 kV.cm−1, respectively. These films showed a ferro-paraelectric transition at close temperatures of Tmax ∼ 605 K, although with higher values of the permittivity for the film processed in oxygen, k ∼ 567 at 10 kHz. The (Pb0.50Ca.50)TiO3 films had a diffuse ferro-paraelectric transition with a relaxor-like character, also with higher k values for the films prepared in oxygen, k ∼ 179 at Tmax ∼ 20 K. The possible use of these materials in silicon integrated multifunctional devices is discussed in this paper.
I. INTRODUCTION
Silicon dioxide (SiO2) is the base material used as the gate dielectric in microelectronic devices. As these devices are progressively scaled down,1 the thickness of the SiO2 gate oxide needs to be reduced. The need of SiO2 layers with thickness below 2 nm is indicated by the semiconductor industry roadmap2 for their use in sub100 nm complementary metal-oxide semiconductor (CMOS) technology. This would increase the computational capability and integration density of the device at lower cost, besides providing the device with lowvoltage operation and low-power consumption. However, this may cause the SiO2 gate oxide to reach its fundamental physical limit, which will cause the device
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Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/JMR.2007.0228 1824 J. Mater. Res., Vol. 22, No. 7, Jul 2007 http://journals.cambridge.org Downloaded: 11 Mar 2015
to fail. Some authors propose new device geometries for continuing the scale-down of silicon devices.3 Other authors suggest the replacement of the SiO2 insulator with high permittivity (high-k) oxides.4 Various high-k metal oxides are being investigated
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