MBE Growth of GaAs on Si through Direct Ge Buffers
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MBE Growth of GaAs on Si through Direct Ge Buffers Xiaojun Yu1,2 , Yu-Hsuan Kuo 2 , Junxian Fu2 , James S Harris, Jr.2 1 Department of Materials Science and Engineering, Stanford University,CA 94305 2 Solid State and Photonics Lab. Stanford University, CISX 126, 420 Via Ortega, Stanford, CA 94305 ABSTRACT The result of GaAs growth on Si using a thin Ge buffer layer (about 0.5µm thick) is presented in this paper. A two-step method with a high temperature anneal between two steps is used to grow the Ge buffer layer. Single phase GaAs is grown on Ge by controlling the growth temperature, substrate miscut and the prelayers. No APD defect is observed by the XTEM and the threading dislocation density of GaAs grown using this method is about 5~10×107 cm-2 . The PL intensity of GaAs is 10× less on Si substrate than on GaAs substrates. INTRODUCTION The realization of low defect density GaAs on Si heteroepitaxy would enable monolithic integration of III-V materials and devices with conventional Si integrated-circuit (IC) technology. It is also desirable to grow high quality GaAs with a very thin layer for the application of high electron mobility transistors on Si. However, GaAs/Si heteroepitaxy has been a difficult challenge with insufficient success for two decades due to its two growth characteristics: large lattice mismatch (4%) and polar-on-nonpolar growth. The strain relaxation process causes the formation of dense threading dislocation. The polar-on-nonpolar growth results in the competition of two phases with different orientation, which creates antiphase defects and induces a rough surface [1]. Tremendous efforts have been made on the direct growth of GaAs on Si[2], and it is difficult to reduce the threading dislocation density (TDD) of the GaAs films to below 108 cm-2 . Different techniques such as AlGaAs/GaAs superlattice buffer [3], strained superlattice and cycling anneal [4] have been used to reduce the threading dislocation but with the compromise of dramatically increase of the surface roughness. The graded Six Ge1-x buffer layer helps to reduce the TDD to below 107 cm-2 , but a thick grading layer is required with the total thickness at 8~10µm[5,6]. The thermal expansion mismatch between Si and epitaxial film is large and a thick SiGe buffers will cause problems during the following processing. The surface is still rough even with a chemical mechanic polishing step included. It is necessary to explore alternate growth approaches to achieve low defect density GaAs with a thin buffer layer. In this paper, a thin strain-relaxed Ge buffer is grown by MBE to provide lattice matched substrates for GaAs growth. The Ge with low TDD is grown on Si through a two-step growth method, and the total thickness of Ge is 0.5µm. Single phase GaAs is grown on Ge buffers by using vicinal Si substrates and controlling the growth temperature and prelayers. Cross-sectional TEM (XTEM) and plain view TEM (PVTEM) are used to investigate the threading dislocation behavior and count the TDD in Ge and GaAs layers. TDD 111A GaAs/
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