Mechanisms of Stacking Fault Growth in SiC PiN Diodes
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Mechanisms of Stacking Fault Growth in SiC PiN Diodes R. E. Stahlbush1, M. E. Twigg1, J. J. Sumakeris2, K. G. Irvine2 and P. A. Losee3 1 Naval Research Laboratory, Washington, DC 20374, USA 2 Cree, Inc., Durham, NC 27703, USA 3 Rensselaer Polytechnic Institute, Troy, NY 12180, USA ABSTRACT The early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150µm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 µm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials’ line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.
INTRODUCTION While SiC has numerous advantages for use in power devices, there are a number of material and processing problems that must be overcome before SiC PiN diodes can be commercially successful. One of the major material problems impeding PiN diode development is the formation of stacking faults during forward-biased operation. The stacking faults are quantumwell recombination centers that decrease carrier lifetime and increase the forward voltage drop [1,2]. The electron-hole recombination within the diode drift region overcomes the kinetic barrier for stacking fault growth by providing the local energy at the site of the bounding partial dislocations and allowing the dislocations to move [3,4]. This paper examines the early, as well as later, stages of stacking fault formation using light emission imaging. The stacking faults examined here originate from within the drift region of the diode and not at substrate-epitaxial or p-n interfaces. This paper also shows that by examining the growth dynamics of the bounding partial dislocations, many properties of the partials as well as the originally present dislocations can be determined.
EXPERIMENTAL DETAILS The epitaxial growth for the diodes in this work consists of a 150µm thick n- drift layer and a p anode layer. All diodes are from the same wafer, which has the standard 8° off-cut angle. +
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The thick drift region was chosen because the eventual goal is to produce diodes with 10 kV blocking voltage. The e
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