Multicast Algorithm for 2D de Bruijn NoCs
The performance of the network is measured in terms of throughput. The throughput and efficiency of interconnect depends on network parameters of the topology. Therefore, topology of any communication networks has an important role to play for efficient d
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Abstract The performance of the network is measured in terms of throughput. The throughput and efficiency of interconnect depends on network parameters of the topology. Therefore, topology of any communication networks has an important role to play for efficient design of network. The De Bruijn topology has the potential to be an interesting option for future generations of System-on-Chip (SoC). Twodimensional (2-D) de Bruijn is proposed for Networks-on-Chips (NoCs) applications. We can improve performance in the two dimensional Bruijn NoCs by improvement of routing algorithm. In this chapter, we have proposed a multicast routing algorithm for 2-D de Bruijn NoCs. The proposed routing algorithm is compared with unicast routing using Xmulator under various traffics conditions. Based on comparison results, the proposed routing has significantly improved the performance and power consumption of the NoC in comparison with unicast routing under light and moderate traffic loads in hot spot and uniform traffics with various message lengths.
1 Introduction With recent advances in VLSI technologies, modern chips can embed large number of processing cores as a multi-core chip. Such multicore chips require efficient communication architecture to provide a high performance connection between the cores. Network-on-Chip (NoC) has been recently proposed as a scalable communication R. Sabbaghi-Nadooshan (B) · A. Malekmohammadi Electrical Engineering Department, Islamic Azad University Central Tehran Branch, Tehran, Iran e-mail: [email protected] A. Malekmohammadi e-mail: [email protected] M. A. Khan Department of Computer Science and Engineering, Sharda University, Greater, Noida, India e-mail: [email protected] M. A. Khan et al. (eds.), Embedded and Real Time System Development: A Software Engineering Perspective, Studies in Computational Intelligence 520, DOI: 10.1007/978-3-642-40888-5_9, © Springer-Verlag Berlin Heidelberg 2014
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architecture for multicore chips [1]. In NoC paradigm, every core communicates with other cores using on-chip channels and an on-chip router. On-chip channels construct a predefined structure called topology. The NoC is a communication centric interconnection approach which provides a scalable infrastructure to interconnect different IPs and sub-systems in a SoC [2]. The NoC can make SoC more structured, reusable and can also improve their performance. Since the communication between the various processing cores will be deciding factor for the performance of such systems, therefore we need to focus on making this communication faster as well as more reliable. Also, the network topology has direct impact on important NoC parameters e.g., network diameter, bisection width, and the routing algorithm [3]. The topology has a great impact on the system performance and reliability. It generally influences network diameter (the length of the maximum shortest path between any two nodes), layout and wiring [4]. These characteristics mainly determine the
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