Multimedia Terminal System-on-Chip Design and Simulation
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Multimedia Terminal System-on-Chip Design and Simulation Ivano Barbieri Department of Biophysical and Electronic Engineering, University of Genova, Via Opera Pia 11A, 16146 Genova, Italy Email: [email protected]
Massimo Bariani Department of Biophysical and Electronic Engineering, University of Genova, Via Opera Pia11A, 16146 Genova, Italy Email: [email protected]
Alessandro Scotto Department of Biophysical and Electronic Engineering, University of Genova, Via Opera Pia 11A, 16146 Genova, Italy Email: [email protected]
Marco Raggio Department of Biophysical and Electronic Engineering, University of Genova, Via Opera Pia 11A, 16146 Genova, Italy Email: [email protected] Received 30 January 2004; Revised 30 March 2005 This paper proposes a design approach based on integrated architectural and system-on-chip (SoC) simulations. The main idea is to have an eļ¬cient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW) digital signal processors (DSPs), the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA) simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported. Keywords and phrases: system-on-chip, multimedia, HW-SW codesign, DSP, simulation, VLIW.
1.
INTRODUCTION
Architecture achievements of the last years followed the HW-SW codesign approach transferring functionalities from hardware to software implementation [5] and moving developers toward system-on-chip (SoC) programmable devices. Otherwise SoC application-driven design seems to be the answer to fulfill multimedia applications requirements [5]. Moreover, thanks to the VLIW [6] architecture approach, it is now possible to design DSP-oriented chips that are standalone processors [7] reaching high degrees of parallelism [8]. Even though a number of general-purpose processors are suitable for DSP tasks, native DSP processors outperform general-purpose devices in terms of their cost-performance ratio and power consumption [9, 10].
In the following, a system-on-chip design based on a dual core DSP architecture will be described. The approach is based on HW-SW codesign, simulating at the same time the instruction set architecture (ISA) and the complete SoC, and taking into account single device performance together with run-time interactions between cores and peripheral devices. 2.
MAIN ISSUE AND RELATED WORK
An HW-SW codesign environment is an application-driven
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