Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs
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Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs Shuu’ichirou Yamamoto1,3, Yusuke Shuto2,3 and Satoshi Sugahara2,3 1 Department of Information Processing, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8502, Japan 2 Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8503, Japan 3 CREST, Japan Science and Technology Agency, 4-1-8 Hon-cho, Kawaguchi 332-0012, Japan ABSTRACT We proposed and computationally analyzed a nonvolatile power-gating field programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spintransfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient powergating (PG). Break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET were proposed, which allows highly efficient PG operations with a fine granularity. INTRODUCTION Over recent years, field programmable gate arrays (FPGAs) are widely used in electronic commercial products. The degree of transistor integration in FPGAs has been increasing year by year according to the progress in the CMOS process technology. However, this situation brings serious power and thermal problems to FPGAs. Clock-gating (CG) and power-gating (PG) techniques are effective at reducing dynamic and static power dissipation in CMOS logic systems, respectively. Although CG has already been applied to FPGAs [1], there are several difficulties to realize PG for FPGAs. The most important problem is data retention during power shutdown. Circuit configuration data in configurable logic blocks (CLBs) of FPGAs and a part of logic operation results in them need to be retained during power shutdown. Nevertheless, conventional technologies cannot achieve complete power shutdown owing to the usage of volatile memories for these data. Therefore, FPGAs with nonvolatile data retention ability are promising for PG. In addition, this nonvolatile ability would lead to PG with an ideal granularity (i.e., high efficiency). Recently, we proposed a nonvolatile power-gating (NVPG) FPGA [2] that is based on pseudo-spin-transistor architecture [3-6] using ordinary MOSFETs and spin-transfertorque magnetic tunnel junctions (STT-MTJs). In this paper, we analyzed the operation and energy performance of the proposed NVPG-FPGA. CIRCUIT CONFIGURATION The NVPG-FPGA is configured using nonvolatile static random memory (NV-SRAM) cells and nonvolatile delay flip-flops (NV-DFFs), as shown in Figures 1(a) and (b). The NVSRAM and NV-DFF circuits are comprised of standard SRAM/FF cells and pseudo-spinMOSFETs (PS-MOSFETs [which are denoted by PSM1 and PSM2
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