Novel Chain Stack Capacitor for 32Mb FeRAM and Beyond
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Novel Chain Stack Capacitor for 32Mb FeRAM and Beyond R. Bruchhaus1, T. Ozaki2, U. Ellerkmann3, J. Lian1, Y. Kumura2, H. Kanaya2, M Yabuki2, T. Tsuchya2, A. Hilliger1, U. Egger1, K. Tomioka2, B. K. Moon1, H. Itokawa2, H. Zhuang1, K. Natori2, G. Beitel1, S. Sugimoto2, K. Yamakawa2, I. Kunishima2, and N. Nagel1 Infineon Toshiba FeRAM Development Alliance (FDA), Toshiba Yokohama Complex, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan, 1 Infineon Technologies Japan K.K., 2Toshiba Corp. Semiconductor Company 3
Institut fuer Werkstoffe der Elektrotechnik II, RWTH Aachen, 52056 Aachen, Germany
ABSTRACT For high density FeRAM devices small cell sizes are essential. The combination of the capacitor on plug (COP) structure with the Chain FeRAMTM cell design is used to develop a 32Mb FeRAM. Based on a 0.2 µm standard CMOS process a silicide capped polysilicon plug is used to contact the bottom electrode of the ferroelectric capacitor to the transistor. The barrier contact to the plug is formed by IrO2/Ir and a sputter deposited PZT (40/60) is used as ferroelectric material. The function of SrRuO3 (SRO) layers at the electrode/PZT interfaces is described in more detail. Double sided SRO results in slightly lower coercive voltage and imprint behavior compared to capacitors without SRO. Double sided SRO is essential to achieve excellent fatigue behavior measured up to 1x1011 switching cycles.
INTRODUCTION Ferroelectric thin films are the key materials within the fabrication of Ferroelectric Random Access Memory Devices (FeRAMs). This new type of memory device combines a unique set of properties such as non-volatility, fast read and write operation as well as low power operation due to the low power read and write possibility. These advantages make them attractive for a wide range of applications including standard non-volatile memory technologies as well as contactless chip cards and mobile applications. To address the non volatile memory market small memory cell sizes and high density must be realized. This is done by 1T/1C operation and the capacitor on plug (COP) structure [1]. If these features are combined with the chain cell design a further reduction in chip size can be achieved. In a Chain FeRAMTM [2] two capacitors are arranged on a common bottom electrode, which is connected to the transistor via a plug. Transis-
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tors and capacitors are connected in parallel forming a chain. For the ferroelectric capacitor a thin film of lead zirconate titanate (PZT) offers high switchable polarization and in combination with SrRuO3 (SRO) layers attached to the PZT/electrode interface excellent fatigue endurance [3]. In this paper the features of the Chain FeRAMTM design and the basic structure of a 32Mb Chain FeRAMTM with COP structure is described. In addition, the function of SRO for the switching behavior as well as for imprint and fatigue is described in more detail.
EXPERIMENTAL DETAILS A 0.2 µm standard CMOS process is used for the 32Mb FeRAM. After formation of the poly silicon plugs and the silicide l
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