Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength
- PDF / 1,663,154 Bytes
- 12 Pages / 612 x 792 pts (letter) Page_size
- 62 Downloads / 156 Views
0970-Y06-05
Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength Shinya Takyu, Tetsuya Kurosawa, Noriko Shimizu, and Susumu Harada TOSHIBA CORPORATION Semiconductor Company, Kawasaki, 212-8583, Japan
ABSTRACT As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thicknesses of 50 to 200 µm, such damage has to be avoided. In this study, the relationship between chip residual damage and chip strength is examined, and novel wafer dicing and thinning technologies that realize an average chip strength have increased from 253 MPa to 1903 MPa are described.
INTRODUCTION Accompanying the rapid progress of the digital network information society, there is strong demand for the high functionality and miniaturization of mobile personal digital assistance devices. As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, the miniaturization of semiconductor devices is necessary. There are two methods of realizing this for systemized semiconductor devices. SOC (System on Chip) integrates different functional cells into one chip and SIP (System in Package) integrates individual chips into one package. SIP easily integrates different types of chip and is manufactured with few technical innovations. Thus, several types of packages have been developed. Most of SIP is fabricated by 3D stacking, which uses thin chips. In the miniaturization of semiconductor devices, wafer dicing and chip thinning technologies are important key technologies. The major problem with thin chips is their decreased breaking force. Note that chip damage has to be prevented to improve chip strength.
Problems in Thinning Chips The manufacturing steps for semiconductor devices are currently classified into steps for patterning semiconductor elements in a wafer, steps for thinning a wafer using a grindstone (BSG; Back Side Grind), and steps for dicing the respective semiconductor elements formed in a wafer into chips and sealing the chips in packages. The wafer thickness during patterning is 725 µm on an 8-inch wafer, 775 µm on a 300mm wafer, and has to be reduced to 50 - 200 µm for 3D stacking. BSG and dicing processes are mechanical processes using diamond grits. These mechanical processes have a high productivity and a low cost as merits; however these pr
Data Loading...
