Optically Active Defects in an InAsP/InP Quantum Well Monolithically Integrated on SrTiO 3 (001)
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1252-J03-01
Optically Active Defects in an InAsP/InP Quantum Well Monolithically Integrated on SrTiO3 (001) J. Cheng1, A. El Akra1, C. Bru-Chevallier1, G. Patriarche2, L. Largeau2, P. Regreny1, G. Hollinger1 and G. Saint-Girons1 1 Université de Lyon; Institut des Nanotechnologies de Lyon INL-UMR5270-CNRS, Ecole Centrale de Lyon, 36 avenue Guy de Collongue, 69134 Ecully, France 2 LPN-UPR20/CNRS, route de Nozay, 91460 Marcoussis, France
ABSTRACT The optical properties of an InAsP/InP quantum well grown on a SrTiO3(001) substrate are analyzed. At 13K, the photoluminescence (PL) yield of the well is comparable to that of a reference well grown on an InP substrate. Increasing the temperature leads to the activation of non-radiative mechanisms for the sample grown on SrTiO3. The main non-radiative channel is related to the thermal excitation of the holes in the first heavy hole excited state, followed by the non-radiative recombination of charge carriers on twins and/or domain boundaries, in the immediate vicinity of the well.
INTRODUCTION Integrating III-V semiconductors on silicon would allow not only combining optoelectronic functionalities with standard Si-based CMOS systems, but also envisaging the use of high mobility III-V channels for fabricating high speed P and N-MOS transistors1. However, the direct growth of III-V on Si is always limited by a too large lattice mismatch. Overcoming this limitation has motivated numerous researches in the past 20 years2,3,4. Various strategies of heterogeneous integration have been proposed, mostly based on wafer fusion of molecular bonding techniques, possibly associated to Smartcut processes5. These techniques have reached an advanced degree of technological maturity, but are still limited by their technological complexity and cost. In recent years, the monolithic integration of crystalline SrTiO3 (STO) on silicon has motivated numerous researches.6,7 In the early 2000’s, Motolora has published interesting but controversial results concerning the monolithic integration of GaAs based transistors on Si using crystalline SrTiO3/Si templates8. On this basis, several groups have proposed using Pr2O3/Si(111)9, or SrHfO3/Si(001)10 templates for the monolithic integration of Ge on Si. In our recent studies, we have described the peculiar behavior of III-V/oxide interface: the III-V material nucleates with its bulk lattice parameter as soon as the growth begins and the mismatch is fully accommodated by a regular array of dislocations confined at the heterointerface11. As a consequence, the growing III-V material does not contain threading dislocations due to plastic relaxation. We have used this peculiarity to grow InP based heterostructures on Gd2O3/Si (111)12 templates and STO (001) substrates11. We have also identified the main challenges related to the
growth of InP on STO, namely a relatively large interface energy and the formation of specific defects such as microtwins and antiphase boundaries13. In this letter, we propose a study of the influence of these defects on the op
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