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Optimization of process parameters of anodic aluminium oxide using an orthogonal array technique for thermal management applications Muralidharan Sundararajan1,2, Shanmugan Subramani3, Mutharasu Devarajan2, and Mariatti Jaafar1,* 1

School of Materials and Mineral Resources Engineering, Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Penang, Malaysia 2 Materials Centre of Excellence (MCoE), PTDI, Western Digital Corporation, Batu Kawan, 14100 Seberang Perai Seletan, Penang, Malaysia 3 School of Physics, Universiti Sains Malaysia (Main Campus), 11800 Minden, Penang, Malaysia

Received: 18 April 2020

ABSTRACT

Accepted: 4 September 2020

The semiconductor packaging field is evolving rapidly due to strong competition in customer demands for increased functionality and performance, further miniaturization, heightened reliability and lower costs. The lifetime reliability and sequential performance of solid-state products are mainly based on the device junction temperature (Tj). The main concerns of efficient thermal management in heat source-based electronic packages are controlling and reducing the device junction temperature and total thermal resistance (Rth). The optimization of process parameters to develop an anodic aluminium oxide nanopore (AAO-np) structure on an Al5052 alloy substrate using an electrochemical process (two-step anodization) is proposed based on the Taguchi orthogonal array (L9). The four major parameters are the electrolyte, anodization time, bath temperature, and applied voltage, which are varied at three different levels. This experiments aim to finalize suitable process parameters and their levels towards optimum Rth and Tj. The morphology of the step-wise preparation of AAO-np structure is discussed for the optimized conditions of 0.3 M oxalic acid, a 3 h anodization time, a 30 V applied voltage, and a bath at room temperature. The resulting AAO-np structure has a pore diameter of 40 to 55 nm and a height of 6 to 7 lm. This formation significantly reduces Rth by 24.58% and Tj by 24.66% for the electronic package compared to a bare Al substrate.

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Springer Science+Business

Media, LLC, part of Springer Nature 2020

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https://doi.org/10.1007/s10854-020-04412-5

J Mater Sci: Mater Electron

1 Introduction The thermal management of heat sources in electronic packages is a crucial area of research and development. In general, such electronic packages consist of a heat source (IC package), a thermal interface material (TIM), and a substrate or heatsink stacked together. These products face a myriad of thermal management challenges after they are assembled together. The junction temperature (Tj) at the active region and the total thermal resistance (Rth) of the entire package are the most critical bottlenecks in semiconductor packaging and must be kept at low as much as possible. As performance and size demands in the electronic industry keep on increasing, an excessive rise in Tj causes thermal runaway and catastrophic failures