Pattern Formation on Silicon-on-Insulator
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JJ1.3.1/KK1.3.1/U1.3.1
Pattern Formation on Silicon-on-Insulator
Frank S. Flack1, Bin Yang1, Minghuang Huang2, Matt Marcus1, Jason Simmons1, Olivia M. Castellini1, Mark A. Eriksson1, Feng Liu2, Max G. Lagally1 1 Materials Research Science and Engineering Center University of Wisconsin Madison, WI 53706, U. S. A. 2 University of Utah SaltLake City, UT 84112, U. S. A. ABSTRACT The strain driven self-assembly of faceted Ge nanocrystals during epitaxy on Si(001) to form quantum dots (QDs) is by now well known. We have also recently provided an understanding of the thermodynamic driving force for directed assembly of QDs on bulk Si (extendable to other QD systems) based on local chemical potential and curvature of the surface. Silicon-on-insulator (SOI) produces unique new phenomena. The essential thermodynamic instability of the very thin crystalline layer (called the template layer) resting on an oxide can cause this layer, under appropriate conditions, to dewet, agglomerate, and self-organize into an array of Si nanocrystals. Using low-energy electron microscopy (LEEM), we observe this process and, with the help of first-principles total-energy calculations, we provide a quantitative understanding of this pattern formation. The Si nanocrystal pattern formation can be controlled by lithographic patterning of the SOI prior to the dewetting process. The resulting patterns of electrically isolated Si nanocrystals can in turn be used as a template for growth of nanostructures, such as carbon nanotubes (CNTs). Finally we show that this growth may be controlled by the flow dynamics of the feed gas across the substrate. INTRODUCTION Silicon-on-insulator substrates are formed by a SiO2 layer sandwiched between a thin crystalline top Si layer (the template layer) and a thick Si (handle) wafer. This arrangement makes it very attractive for use as a substrate in the fabrication of low-power, low-voltage devices and advanced devices requiring thin geometries. As devices shrink in lateral size, the template layer must shrink correspondingly in order to maintain the benefits of an SOI structure. This ultra-thin configuration, however, is only quasi-stable, thermodynamically. As the template film is made thinner, the surface free energy begins to overcome the kinetic limitations on its geometry [1-4]. Upon heating, such films may act to minimize their surface free energy by changing their morphology, typically via dewetting the unstable interface and agglomeration into 3D nanocrystals (see review [5]). Such behavior has obvious implications for semiconductor device processing, but can potentially be exploited to generate useful nanostructures as well. Earlier work on SOI decomposition has noted that template layers on the order of tens of nanometers in thickness will agglomerate in patterns that are aligned in the directions, but has not been able to explain this behavior. This study proposes a mechanism describing the
JJ1.3.2/KK1.3.2/U1.3.2
source of ordering of nanocrystals into networks by thermal dewetting of SOI and present
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