Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors
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Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors Mustafa B. Akbulut1, Helena Silva1 and Ali Gokirmak1 1 Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269
ABSTRACT Accumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges. INTRODUCTION Line edge roughness (LER) has been a limiting factor in gate scaling of silicon MOSFETs [2]. Recently, however, with the introduction of lithographically defined thin body devices such as FinFET and Tri-gate FETs, LER started to affect the active region of MOSFETs as well [3, 4]. Grazing incidence ion beams [5] and high temperature hydrogen annealing [6] have been proposed to reduce LER, which was shown to result in significant silicon diffusion with LER reduction from ~ 2.8 nm to 0.8 nm. In this work, instead of focusing on reduction of LER itself, we study an electrostatic method to reduce the effects of LER, through the use of a guard-ring gate surrounding the body of the FET. THEORY The pentagate approach We have previously shown that gating the body of a Si MOSFET with a side-gate biased such as to accumulate the Si body (Figure 1) reduces off-state leakage currents by countering the effect of positive fixed charges and passivating defects at the at the Si body / dielectric interface and enables significant threshold voltage tuning [1].
Figure 1. 3D electron density graph of a pFET with applied side-gate bias. Red indicates a density of 1.1x1021 cm-3. In a case where the body edge is severely non-uniform due to LER, the side-gate follows the edges of the body. The normal electric field converges on convexities while diverging on concavities on the side surfaces, resulting in stronger accumulation of majority carriers in convex portions, electrostatically smoothing the channel pathway for the minority charge carriers (Figure 2). Polysilicon side-gate
SiO2 Si body Diverging E-Field Converging E-Field Figure 2. Cross-section of a simulated silicon body surrounded by a polysilicon side-gate. Diverging and converging electric fields (arrows) follow LER and electric field intensity (color) is higher on wider regions of the body.
Simulation We have simulated 3-D tri-gate n- and p-FET structures with LER to study the effect of the side-gate on the device characteristics, using Synopsys Sentaurus TCAD tools [7]. The simulation tools were used to create various sinusoidal LER cases with varying amplitudes imposed on a nominal width (shown in Table I). An idealized fabrication process was simulated, after which the electrical characteristics of the resulting devices were analyzed.
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