Performance of Optimized Reversible Vedic Multipliers
Signal processing applications involve in many arithmetic operations. High speed arithmetic operations play an important role in these applications. Multipliers are often considered as the basic building blocks of digital signal processors (DSP). The spee
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Abstract Signal processing applications involve in many arithmetic operations. High speed arithmetic operations play an important role in these applications. Multipliers are often considered as the basic building blocks of digital signal processors (DSP). The speed of the multiplier corresponds to DSP. Multiplication is the basic operation to be performed in DSP. In order to implement these multiplications many algorithms are used. In this paper, few algorithms are discussed to implement multiplication. The algorithm discussed in this paper is the most ancient methodology used by Aryans. In this paper reversible Vedic multiplier is proposed using Urdhva Tiryakbhyam (UT) sutra and a comparative study reveals and suggests different logics pertaining to different profile considerations such as power and area. Keywords Vedic mathematics power Area
Algorithms
Urdhva Tiryakbhyam
Low
A. Sai Ramya (&) B.S.S.V.Ramesh Babu E. Srikala M. Pavan P. Unita A.V.S. Swathi Department of ECE, Raghu Institute of Technology, Visakhapatnam, India e-mail: [email protected] B.S.S.V.Ramesh Babu e-mail: [email protected] E. Srikala e-mail: [email protected] M. Pavan e-mail: [email protected] P. Unita e-mail: [email protected] A.V.S. Swathi e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2017 S.C. Satapathy et al. (eds.), Computer Communication, Networking and Internet Security, Lecture Notes in Networks and Systems 5, DOI 10.1007/978-981-10-3226-4_60
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1 Introduction Generally when two binary numbers are to be multiplied a binary multiplier is used. Binary multiplier is a significant block in every digital signal processors. These are widely used in Fourier transform and Convolutions. The processor speed can be greatly improved by improving multiplication operation, as much of processor speed is dependent on multiplication operation. Algorithms like such as array, booth, carry save and Wallace tree are used to implement multiplication. Among these the array algorithm reported very less computational time. This is because of partial products which are computed independently. Array multiplier for unsigned numbers results in reduced silicon area without effecting speed and power [1, 2]. In case of Booth algorithm the partial products obtained are less. Even though partial products are minimum in order to improve speed of the multiplication operation large booth arrays are required which further require large partial sum and partial carry registers. Booth algorithm is structured for a n m multiplication where n can reach up to 126 bits [2, 3]. The carry-save technique is used in the Booth encoder, the Booth multiplier, and the accumulator sections to ensure the fastest possible implementation [3, 4]. The compression ratio of 3:2 is achieved using Wallace tree. The utilization of carry look ahead adder (CLA) results in an increase of speed. It is independent on the number of bits of the two operands [5]. This paper has been organized as follows. S
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