Phase-change memory cycling endurance
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Introduction In an ideal world, one would be able to cycle a phase-change memory device indefinitely, alternating between SET pulses for the crystalline phase (low resistance) and RESET pulses for the amorphous phase (high resistance), with the switching conditions and the resulting resistance states remaining completely stable. In practice, however, device characteristics change during cycling, at first slowly and then more rapidly, leading eventually to one of two failure modes: stuck-SET, in which the device stays in a low resistance state and refuses to RESET, or stuck-RESET, in which the device stays in a highresistance state and refuses to SET.1,2 At the early stages of phase-change memory research, it was suggested that the cycling endurance could be as high as 1012.3 However, various implementation efforts have resulted in agreement that the empirical endurance limit of typical phase-change memory cells is the range of 106–109, which is much better than NAND flash memory, but less than the desired limit of 1012 or even 1015 needed for working memory applications, where frequent and constant memory access is required. The improvement of cycling endurance is the main issue to be addressed for phase-change memory products4 in order to expand and dominate the persistent memory market, which has the potential to grow to more than USD$1 billion/ year in the next several years.5
It has been speculated that unlimited phase-change memory cycling endurance would not be possible because of the high temperatures (melting temperature typically at ∼900 K) that phase-change memory cells experience during the write operation. To raise the temperature above the melting temperature through Joule heating, the current density needs to be quite high, typically ∼10 MA/cm2, at which levels electromigration can occur in metal interconnects.6 Also, the frequent volume changes due to the rise in temperature and changes in phases, which is roughly 7% between crystalline and amorphous Ge2Sb2Te5, for example,7 could cause complex stress distributions in the phasechange memory cell. Successful R&D of various phase-change materials (PCMs) such as Ge2Sb2Te5 and GeTe has been able to address various important issues in phase-change memory because lots of key characteristics of phase-change memories (e.g., writing speed, retention, and programming power) are directly governed by corresponding materials properties (e.g., crystallization speed, crystallization temperature, and thermal conductivity, respectively). However, it has not been possible to identify a single or even a couple of materials properties that directly govern the cycling endurance. In the following, we discuss and introduce various findings and models regarding the cycling endurance, such as failure mechanisms, key experimental results, and strategies, in order to improve phase-change memory endurance.
SangBum Kim, Department of Materials Science and Engineering, Seoul National University, Republic of Korea, [email protected] Geoffrey W. Burr, IBM Research–Almaden, US
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