PN Sequence Preestimator Scheme for DS-SS Signal Acquisition Using Block Sequence Estimation
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PN Sequence Preestimator Scheme for DS-SS Signal Acquisition Using Block Sequence Estimation Kwangmin Hyun Division of Engineering, Wonju National College, Wonju-Si, Gangwon-Do 220-711, Korea Email: [email protected]
Dongweon Yoon Division of Electrical and Computer Engineering, Hanyang University, Seoul 133-791, Korea Email: [email protected]
Sang Kyu Park Division of Electrical and Computer Engineering, Hanyang University, Seoul 133-791, Korea Email: [email protected] Received 10 February 2004; Revised 12 June 2004; Recommended for Publication by Xiang-Gen Xia An m-sequence (PN sequence) preestimator scheme for direct-sequence spread spectrum (DS-SS) signal acquisition by using block sequence estimation (BSE) is proposed and analyzed. The proposed scheme consists of an estimator and a verifier which work according to the PN sequence chip clock, and provides not only the enhanced chip estimates with a threshold decision logic and one-chip error correction among the first m received chips, but also the reliability check of the estimates with additional decision logic. The probabilities of the estimator and verifier operations are calculated. With these results, the detection, the false alarm, and the missing probabilities of the proposed scheme are derived. In addition, using a signal flow graph, the average acquisition time is calculated. The proposed scheme can be used as a preestimator and easily implemented by changing the internal signal path of a generally used digital matched filter (DMF) correlator or any other correlator that has a lot of sampling data memories for sampled PN sequence. The numerical results show rapid acquisition performance in a relatively good CNR. Keywords and phrases: sequential estimation, PN sequence, acquisition, spread spectrum, digital matched filter.
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INTRODUCTION
PN sequence acquisition is a precondition for stable and reliable spread spectrum communication. The research on PN sequence acquisition has been continuing for more than 20 years to improve its performance, stability, and acquisition speed [1, 2]. There are two representative methods for the acquisition of a PN sequence. One is a sequential estimation method that uses one of the important characteristics of the PN sequence generation with linear feedback shift register (LFSR) structure. That is, if m chips of the PN sequence can be estimated correctly from the received signal, these chips can be loaded into the m-shift-register generator to synchronize the system. In 1977, Ward and Yiu enhanced this method with recursive-aided sequential estimation [3]. In spite of its simple structure and rapid acquisition performance, this method cannot be used for low SNR radio environment because of the performance degradation and its instability. Several studies [4, 5, 6] have been done with a majority-
logic decoder to enhance the acquisition performance using a large number of parity-check sums for each chip. Recently, a seed-accumulating sequential estimation scheme [7] has been proposed by accumulating each chip
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