Polysilicon/Silicon Interfaces: Effect of Processing Parameters on Physical and Electrical Properties
- PDF / 416,806 Bytes
- 6 Pages / 420.48 x 639 pts Page_size
- 117 Downloads / 240 Views
POLYSILICON/SILICON INTERFACES: EFFECT OF PROCESSING PARAMETERS ON PHYSICAL AND ELECTRICAL PROPERTIES
K. SRIKRISHNA, M. MOINPOUR AND B. LANDAU Technology Development, National Semiconductor Corporation, Santa Clara CA 95051.
ABSTRACT An arsenic doped polysilicon emitter structure is widely used as an important technology for high speed BiPolar and BiCMOS VLSI devices. The electrical behavior of such emitters is dictated to a large degree by the structure of the polysilicon/silicon interface and the extent of any interfacial oxide. In particular the contact resistance of n+ and p+ diffused regions of the polysilicon is sensitive to the interfacial structure. The microstructure of the polysilicon, in addition to the interface, dictates the junction depth and electrical properties and is determined by the deposition conditions and subsequent doping and annealing processes. The interface itself is defined largely by the cleaning procedure and the initial stages of the deposition process. In this paper we report the effects of process variables, such as deposition temperature, doping and annealing times and temperatures and pre-cleans on the microstructure and electrical properties of poly-emitters. INTRODUCTION The use of low pressure chemical vapor deposited polysilicon as an emitter contact for transistors in Bipolar and BiCMOS technologies has become prevalent. The ability to implant dual species into the polysilicon and diffuse them simultaneously to form high speed shallow junctions makes poly emitter technology very attractive [1]. The interface between the deposited polysilicon and single crystalline substrate plays a critical role in governing the electrical behavior, in particular the current gain (B)and the base current of these bipolar transistors [2]. Atomically clean interfaces between the polysilicon and the substrate lead to the epitaxial realignment of the polysilicon [3]; interfaces that have a layer of thermal or chemical oxide, act as a diffusion barrier and prevent the implanted species from diffusing into the substrate [4] and hamper the formation of shallow junctions. Control of this interface has been attempted by cleaning the substrate with an aqueous etchant such as hydrofluoric acid [3] prior to polysilicon deposition or by growing a controlled amount of thermal oxide or deposited CVD nitride [4]. An alternate approach has been to subject the device to high temperature anneals after polysilicon deposition in a rapid thermal annealer [5] or a conventional furnace [6]. All these methods of interfacial control suffer from various limitations such as thermal budget (qDt) constraints, time restrictions between precleans and polysilicon deposition limiting manufacturability and formation of a native chemical oxide subsequent to any cleans leading to a high contact resistance. The current work reports on the effects of the processing parameters of the preclean and the polysilicon deposition on the electrical behavior of Kelvin resistance structures. Kelvin resistance structures were chosen as the t
Data Loading...
